# Performance monitoring events for processors based on the Sandy Bridge microarchitecture.
# Applies to processors with DisplayFamily_DisplayModel of 06_2AH and 06_2DH.
# See Table 19-16 of Intel's "System Programming Guide" (Jan. 2019)

0E.01 UOPS_ISSUED.ANY
B1.01 UOPS_DISPATCHED.THREAD
C2.01 UOPS_RETIRED.ALL
A1.01 UOPS_DISPATCHED_PORT.PORT_0
A1.02 UOPS_DISPATCHED_PORT.PORT_1
A1.0C UOPS_DISPATCHED_PORT.PORT_2
A1.30 UOPS_DISPATCHED_PORT.PORT_3
A1.40 UOPS_DISPATCHED_PORT.PORT_4
A1.80 UOPS_DISPATCHED_PORT.PORT_5
C4.00 BR_INST_RETIRED.ALL_BRANCHES
C5.04 BR_MISP_RETIRED.ALL_BRANCHES
D1.01 MEM_LOAD_UOPS_RETIRED.L1_HIT
D1.02 MEM_LOAD_UOPS_RETIRED.L2_HIT
D1.04 MEM_LOAD_UOPS_RETIRED.LLC_HIT
D1.20 MEM_LOAD_UOPS_RETIRED.LLC_MISS