mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-09-07 02:10:12 +02:00
285 lines
13 KiB
Python
Executable File
285 lines
13 KiB
Python
Executable File
#!/apps/python/3.5-anaconda/bin/python
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import os
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from subprocess import call
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from math import ceil
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from Params import *
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class Testcase(object):
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##------------------Constant variables--------------------------
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# Lookup tables for regs
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gprs64 = ['rax', 'rbx', 'rcx', 'rdx', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15']
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gprs32 = ['eax', 'ebx', 'ecx', 'edx', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d']
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gprs16 = ['ax', 'bx', 'cx', 'dx', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w']
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gprs8 = ['al', 'bl', 'cl', 'dl', 'r9l', 'r10l', 'r11l', 'r12l', 'r13l', 'r14l', 'r15l']
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fpus = ['st0', 'st1', 'st2', 'st3', 'st4', 'st5', 'st6', 'st7']
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mmxs = ['mm0', 'mm1', 'mm2', 'mm3', 'mm4', 'mm5', 'mm6', 'mm7']
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ks = ['k0', 'k1', 'k2', 'k3', 'k4', 'k5', 'k6', 'k7']
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bnds = ['bnd0', 'bnd1', 'bnd2', 'bnd3', 'bnd4', 'bnd5', 'bnd6', 'bnd7']
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xmms = ['xmm0', 'xmm1', 'xmm2', 'xmm3', 'xmm4', 'xmm5', 'xmm6', 'xmm7', 'xmm8', 'xmm9',
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'xmm10', 'xmm11', 'xmm12', 'xmm13', 'xmm14', 'xmm15']
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ymms = ['ymm0', 'ymm1', 'ymm2', 'ymm3', 'ymm4', 'ymm5', 'ymm6', 'ymm7', 'ymm8', 'ymm9',
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'ymm10', 'ymm11', 'ymm12', 'ymm13', 'ymm14', 'ymm15']
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zmms = ['zmm0', 'zmm1', 'zmm2', 'zmm3', 'zmm4', 'zmm5', 'zmm6', 'zmm7', 'zmm8', 'zmm9',
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'zmm10', 'zmm11', 'zmm12', 'zmm13', 'zmm14', 'zmm15']
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# Lookup table for memory
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mems = ['[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]']
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# Lookup table for immediates
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imds = ['1', '2', '13', '22', '8', '78', '159', '222', '3', '9', '5', '55', '173', '317', '254', '255']
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# TODO Differentiate between AVX512 (with additional xmm16-31) and the rest
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# ...
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# ...
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# end TODO
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ops = {'gpr64':gprs64, 'gpr32':gprs32, 'gpr16':gprs16, 'gpr8':gprs8, 'fpu':fpus, 'mmx':mmxs, 'k':ks, 'bnd':bnds, 'xmm':xmms, 'ymm':ymms, 'zmm':zmms, 'mem':mems, 'imd':imds}
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# Create Single Precision 1.0
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sp1 = '\t\t# create SP 1.0\n'
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sp1 += '\t\tvpcmpeqw xmm0, xmm0, xmm0\n'
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sp1 += '\t\tvpslld xmm0, xmm0, 25\t\t\t# logical left shift: 11111110..0 (25=32-(8-1))\n'
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sp1 += '\t\tvpsrld xmm0, xmm0, 2\t\t\t# logical right shift: 1 bit for sign; leading mantissa bit is zero\n'
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sp1 += '\t\t# copy SP 1.0\n'
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# Create Double Precision 1.0
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dp1 = '\t\t# create DP 1.0\n'
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dp1 += '\t\tvpcmpeqw xmm0, xmm0, xmm0\t\t# all ones\n'
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dp1 += '\t\tvpsllq xmm0, xmm0, 54\t\t\t# logical left shift: 11111110..0 (54=64-(10-1))\n'
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dp1 += '\t\tvpsrlq xmm0, xmm0, 2\t\t\t# logical right shift: 1 bit for sign; leading mantissa bit is zero\n'
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# Create epilogue
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done = ('done:\n'
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'\t\tmov\trsp, rbp\n'
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'\t\tpop\trbp\n'
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'\t\tret\n'
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'.size latency, .-latency')
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##----------------------------------------------------------------
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# Constructor
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def __init__(self, _mnemonic, _param_list, _num_instr='12'):
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self.instr = _mnemonic.lower()
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self.param_list = _param_list
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# num_instr must be an even number
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self.num_instr = str(ceil(int(_num_instr)/2)*2)
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# Check for the number of operands and initialise the GPRs if necessary
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self.op_a, self.op_b, self.op_c, self.gprPush, self.gprPop, self.zeroGPR, self.copy = self.__define_operands()
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self.num_operands = len(self.param_list)
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# Create asm header
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self.def_instr, self.ninstr, self.init, self.expand = self.__define_header()
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# Create latency and throughput loop
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self.loop_lat = self.__define_loop_lat()
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self.loop_thrpt = self.__define_loop_thrpt()
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def write_testcase(self):
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regs = self.param_list
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extension = ''
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# Add operands
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sep1 = '_' if (self.num_operands > 1) else ''
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sep2 = '_' if (self.num_operands > 2) else ''
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extension += ('-'+(self.op_a if ('gpr' not in self.op_a) else 'r'+self.op_a[3:]) + sep1 +
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(self.op_b if ('gpr' not in self.op_b) else 'r'+self.op_b[3:]) + sep2 +
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(self.op_c if ('gpr' not in self.op_c) else 'r'+self.op_c[3:]))
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# Write latency file
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call(['mkdir', '-p', 'testcases'])
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f = open('./testcases/'+self.instr+extension+'.S', 'w')
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data = (self.def_instr+self.ninstr+self.init+self.dp1+self.expand+self.gprPush+self.zeroGPR+self.copy+self.loop_lat+self.gprPop+self.done)
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f.write(data)
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f.close()
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# Write throughput file
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f = open('./testcases/'+self.instr+extension+'-TP.S', 'w')
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data = (self.def_instr+self.ninstr+self.init+self.dp1+self.expand+self.gprPush+self.zeroGPR+self.copy+self.loop_thrpt+self.gprPop+self.done)
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f.write(data)
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f.close()
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# Check operands
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def __define_operands(self):
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oprnds = self.param_list
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op_a, op_b, op_c = ('', '', '')
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gprPush, gprPop, zeroGPR = ('', '', '')
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if(isinstance(oprnds[0], Register)):
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op_a = oprnds[0].reg_type.lower()
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elif(isinstance(oprnds[0], MemAddr)):
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op_a = 'mem'
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elif(isinstance(oprnds[0], Parameter) and oprnds[0].print() == 'IMD'):
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op_a = 'imd'
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if(op_a == 'gpr'):
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gprPush, gprPop, zeroGPR = self.__initialise_gprs()
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op_a += str(oprnds[0].size)
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if(len(oprnds) > 1):
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if(isinstance(oprnds[1], Register)):
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op_b = oprnds[1].reg_type.lower()
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elif(isinstance(oprnds[1], MemAddr)):
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op_b = 'mem'
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elif(isinstance(oprnds[1], Parameter) and oprnds[1].print() == 'IMD'):
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op_b = 'imd'
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if(op_b == 'gpr'):
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op_b += str(oprnds[1].size)
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if('gpr' not in op_a):
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gprPush, gprPop, zeroGPR = self.__initialise_gprs()
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if(len(oprnds) == 3):
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if(isinstance(oprnds[2], Register)):
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op_c = oprnds[2].reg_type.lower()
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elif(isinstance(oprnds[2], MemAddr)):
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op_c = 'mem'
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elif(isinstance(oprnds[2], Parameter) and oprnds[2].print() == 'IMD'):
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op_c = 'imd'
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if(op_c == 'gpr'):
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op_c += str(oprnds[2].size)
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if(('gpr' not in op_a) and ('gpr'not in op_b)):
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gprPush, gprPop, zeroGPR = self.__initialise_gprs()
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if(len(oprnds) == 1 and isinstance(oprnds[0], Register)):
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copy = self.__copy_regs(oprnds[0])
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elif(len(oprnds) > 1 and isinstance(oprnds[1], Register)):
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copy = self.__copy_regs(oprnds[1])
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elif(len(oprnds) > 2 and isinstance(oprnds[2], Register)):
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copy = self.__copy_regs(oprnds[1])
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else:
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copy = ''
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return (op_a, op_b, op_c, gprPush, gprPop, zeroGPR, copy)
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# Initialise 11 general purpose registers and set them to zero
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def __initialise_gprs(self):
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gprPush = ''
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gprPop = ''
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zeroGPR = ''
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for reg in self.gprs64:
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gprPush += '\t\tpush {}\n'.format(reg)
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for reg in reversed(self.gprs64):
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gprPop += '\t\tpop {}\n'.format(reg)
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for reg in self.gprs64:
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zeroGPR += '\t\txor {}, {}\n'.format(reg, reg)
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return (gprPush, gprPop, zeroGPR)
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# Copy created values in specific register
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def __copy_regs(self, reg):
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copy = '\t\t# copy DP 1.0\n'
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# Different handling for GPR, MMX and SSE/AVX registers
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if(reg.reg_type == 'GPR'):
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][1])
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copy += '\t\t# Create DP 2.0\n'
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copy += '\t\tadd {}, {}\n'.format(self.ops['gpr64'][1], self.ops['gpr64'][0])
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copy += '\t\t# Create DP 0.5\n'
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copy += '\t\tdiv {}\n'.format(self.ops['gpr64'][0])
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copy += '\t\tmovq {}, {}\n'.format(self.ops['gpr64'][2], self.ops['gpr64'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][0])
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elif(reg.reg_type == 'MMX'):
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['mmx'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['mmx'][1])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][0])
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copy += '\t\t# Create DP 2.0\n'
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copy += '\t\tadd {}, {}\n'.format(ops['mmx'][1], ops['mmx'][0])
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copy += '\t\t# Create DP 0.5\n'
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copy += '\t\tdiv {}\n'.format(self.ops['gpr64'][0])
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copy += '\t\tmovq {}, {}\n'.format(self.ops['mmx'][2], self.ops['gpr64'][0])
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elif(reg.reg_type == 'XMM' or reg.reg_type == 'YMM' or reg.reg_type == 'ZMM'):
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key = reg.reg_type.lower()
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copy += '\t\tvmovaps {}, {}\n'.format(self.ops[key][0], self.ops[key][0])
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copy += '\t\tvmovaps {}, {}\n'.format(self.ops[key][1], self.ops[key][0])
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copy += '\t\t# Create DP 2.0\n'
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copy += '\t\tvaddpd {}, {}, {}\n'.format(self.ops[key][1], self.ops[key][1], self.ops[key][1])
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copy += '\t\t# Create DP 0.5\n'
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copy += '\t\tvdivpd {}, {}, {}\n'.format(self.ops[key][2], self.ops[key][0], self.ops[key][1])
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else:
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copy = ''
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return copy
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def __define_header(self):
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def_instr = '#define INSTR '+self.instr+'\n'
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ninstr = '#define NINST '+self.num_instr+'\n'
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pi = ('PI:\n'
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'.long 0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' #128 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' #256 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' #384 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9\n') #512 bit
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init = ('#define N edi\n' \
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'#define i r8d\n\n\n'
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'.intel_syntax noprefix\n'
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'.globl ninst\n'
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'.data\n'
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'ninst:\n'
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'.long NINST\n'
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'.align 32\n'
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+pi+
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'.text\n'
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'.globl latency\n'
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'.type latency, @function\n'
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'.align 32\n'
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'latency:\n'
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'\t\tpush rbp\n'
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'\t\tmov rbp, rsp\n'
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'\t\txor i, i\n'
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'\t\ttest N, N\n'
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'\t\tjle done\n')
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# Expand to AVX(512) if necessary
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expand = ''
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if(self.op_a == 'ymm' or self.op_b == 'ymm' or self.op_c == 'ymm'):
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expand = ('\t\t# expand from SSE to AVX\n'
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'\t\tvinsertf128 ymm0, ymm0, xmm0, 0x1\n')
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if(self.op_a == 'zmm' or self.op_b == 'zmm' or self.op_c == 'zmm'):
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expand = ('\t\t# expand from SSE to AVX\n'
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'\t\tvinsertf128 ymm0, ymm0, xmm0, 0x1\n'
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'\t\t# expand from AVX to AVX512\n'
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'\t\tvinsert64x4 zmm0, zmm0, ymm0, 0x1\n')
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return (def_instr, ninstr, init, expand)
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# Create latency loop
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def __define_loop_lat(self):
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loop_lat = ('loop:\n'
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'\t\tinc i\n')
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if(self.num_operands == 1):
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for i in range(0, int(self.num_instr)):
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loop_lat += '\t\tINSTR {}\n'.format(self.ops[self.op_a][0])
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elif(self.num_operands == 2 and self.op_a == self.op_b):
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for i in range(0, int(self.num_instr), 2):
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0], self.ops[self.op_b][1])
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_b][1], self.ops[self.op_b][0])
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elif(self.num_operands == 2 and self.op_a != self.op_b):
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for i in range(0, int(self.num_instr), 2):
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0], self.ops[self.op_b][0])
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0], self.ops[self.op_b][0])
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elif(self.num_operands == 3 and self.op_a == self.op_b):
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for i in range(0, int(self.num_instr), 2):
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loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][0], self.ops[self.op_b][1], self.ops[self.op_c][0])
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loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][1], self.ops[self.op_b][0], self.ops[self.op_c][0])
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elif(self.num_operands == 3 and self.op_a == self.op_c):
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for i in range(0, int(self.num_instr), 2):
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loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][0], self.ops[self.op_b][0], self.ops[self.op_c][0])
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loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][1], self.ops[self.op_b][0], self.ops[self.op_c][0])
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loop_lat += ('\t\tcmp i, N\n'
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'\t\tjl loop\n')
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return loop_lat
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# Create throughput loop
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def __define_loop_thrpt(self):
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loop_thrpt = ('loop:\n'
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'\t\tinc i\n')
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ext = ''
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ext1 = False
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ext2 = False
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if(self.num_operands == 2):
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ext1 = True
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if(self.num_operands == 3):
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ext1 = True
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ext2 = True
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for i in range(0, int(self.num_instr)):
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if(ext1):
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ext = ', {}'.format(self.ops[self.op_b][i%3])
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if(ext2):
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ext += ', {}'.format(self.ops[self.op_c][i%3])
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regNum = (i%(len(self.ops[self.op_a])-3))+3
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loop_thrpt += '\t\tINSTR {}{}\n'.format(self.ops[self.op_a][regNum], ext)
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loop_thrpt += ('\t\tcmp i, N\n'
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'\t\tjl loop\n')
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return loop_thrpt
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def __is_in_dir(self, name, path):
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for root, dirs, files in os.walk(path):
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if name in files:
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return True
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return False
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