mirror of
https://github.com/RRZE-HPC/OSACA.git
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337 lines
14 KiB
Python
Executable File
337 lines
14 KiB
Python
Executable File
#!/usr/bin/env python3
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from itertools import chain
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from osaca import utils
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from osaca.parser import AttrDict, ParserAArch64, ParserX86ATT
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from .hw_model import MachineModel
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class INSTR_FLAGS:
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"""
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Flags used for unknown or special instructions
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"""
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LD = "is_load_instruction"
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TP_UNKWN = "tp_unknown"
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LT_UNKWN = "lt_unknown"
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NOT_BOUND = "not_bound"
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HIDDEN_LD = "hidden_load"
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HAS_LD = "performs_load"
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HAS_ST = "performs_store"
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class ISASemantics(object):
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GAS_SUFFIXES = "bswlqt"
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def __init__(self, isa, path_to_yaml=None):
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self._isa = isa.lower()
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path = path_to_yaml or utils.find_datafile("isa/" + self._isa + ".yml")
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self._isa_model = MachineModel(path_to_yaml=path)
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if self._isa == "x86":
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self._parser = ParserX86ATT()
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elif self._isa == "aarch64":
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self._parser = ParserAArch64()
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def process(self, instruction_forms):
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"""Process a list of instruction forms."""
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for i in instruction_forms:
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self.assign_src_dst(i)
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# get ;parser result and assign operands to
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# - source
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# - destination
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# - source/destination
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def assign_src_dst(self, instruction_form):
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"""Update instruction form dictionary with source, destination and flag information."""
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# if the instruction form doesn't have operands or is None, there's nothing to do
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if instruction_form["operands"] is None or instruction_form["instruction"] is None:
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instruction_form["semantic_operands"] = AttrDict(
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{"source": [], "destination": [], "src_dst": []}
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)
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return
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# check if instruction form is in ISA yaml, otherwise apply standard operand assignment
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# (one dest, others source)
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isa_data = self._isa_model.get_instruction(
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instruction_form["instruction"], instruction_form["operands"]
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)
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if (
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isa_data is None
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and self._isa == "x86"
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and instruction_form["instruction"][-1] in self.GAS_SUFFIXES
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):
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# Check for instruction without GAS suffix
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isa_data = self._isa_model.get_instruction(
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instruction_form["instruction"][:-1], instruction_form["operands"]
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)
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operands = instruction_form["operands"]
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op_dict = {}
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assign_default = False
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if isa_data:
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# load src/dst structure from isa_data
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op_dict = self._apply_found_ISA_data(isa_data, operands)
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else:
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# Couldn't found instruction form in ISA DB
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assign_default = True
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# check for equivalent register-operands DB entry if LD/ST
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if any(["memory" in op for op in operands]):
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operands_reg = self.substitute_mem_address(instruction_form["operands"])
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isa_data_reg = self._isa_model.get_instruction(
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instruction_form["instruction"], operands_reg
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)
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if (
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isa_data_reg is None
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and self._isa == "x86"
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and instruction_form["instruction"][-1] in self.GAS_SUFFIXES
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):
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# Check for instruction without GAS suffix
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isa_data_reg = self._isa_model.get_instruction(
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instruction_form["instruction"][:-1], operands_reg
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)
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if isa_data_reg:
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assign_default = False
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op_dict = self._apply_found_ISA_data(isa_data_reg, operands)
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if assign_default:
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# no irregular operand structure, apply default
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op_dict["source"] = self._get_regular_source_operands(instruction_form)
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op_dict["destination"] = self._get_regular_destination_operands(instruction_form)
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op_dict["src_dst"] = []
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# post-process pre- and post-indexing for aarch64 memory operands
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if self._isa == "aarch64":
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for operand in [op for op in op_dict["source"] if "memory" in op]:
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post_indexed = (
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"post_indexed" in operand["memory"] and operand["memory"]["post_indexed"]
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)
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pre_indexed = (
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"pre_indexed" in operand["memory"] and operand["memory"]["pre_indexed"]
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)
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if post_indexed or pre_indexed:
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op_dict["src_dst"].append(
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AttrDict.convert_dict(
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{
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"register": operand["memory"]["base"],
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"pre_indexed": pre_indexed,
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"post_indexed": post_indexed,
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}
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)
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)
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for operand in [op for op in op_dict["destination"] if "memory" in op]:
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post_indexed = (
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"post_indexed" in operand["memory"] and operand["memory"]["post_indexed"]
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)
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pre_indexed = (
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"pre_indexed" in operand["memory"] and operand["memory"]["pre_indexed"]
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)
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if post_indexed or pre_indexed:
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op_dict["src_dst"].append(
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AttrDict.convert_dict(
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{
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"register": operand["memory"]["base"],
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"pre_indexed": pre_indexed,
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"post_indexed": post_indexed,
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}
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)
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)
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# store operand list in dict and reassign operand key/value pair
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instruction_form["semantic_operands"] = AttrDict.convert_dict(op_dict)
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# assign LD/ST flags
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instruction_form["flags"] = (
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instruction_form["flags"] if "flags" in instruction_form else []
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)
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if self._has_load(instruction_form):
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instruction_form["flags"] += [INSTR_FLAGS.HAS_LD]
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if self._has_store(instruction_form):
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instruction_form["flags"] += [INSTR_FLAGS.HAS_ST]
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def get_reg_changes(self, instruction_form, only_postindexed=False):
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"""
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Returns register changes, as dict, for insruction_form, based on operation defined in isa.
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Empty dict if no changes of registers occured. None for registers with unknown changes.
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If only_postindexed is True, only considers changes due to post_indexed memory references.
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"""
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if instruction_form.get("instruction") is None:
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return {}
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dest_reg_names = [
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op.register.get("prefix", "") + op.register.name
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for op in chain(
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instruction_form.semantic_operands.destination,
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instruction_form.semantic_operands.src_dst,
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)
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if "register" in op
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]
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isa_data = self._isa_model.get_instruction(
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instruction_form["instruction"], instruction_form["operands"]
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)
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if (
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isa_data is None
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and self._isa == "x86"
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and instruction_form["instruction"][-1] in self.GAS_SUFFIXES
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):
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# Check for instruction without GAS suffix
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isa_data = self._isa_model.get_instruction(
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instruction_form["instruction"][:-1], instruction_form["operands"]
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)
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if only_postindexed:
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for o in instruction_form.operands:
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if "post_indexed" in o.get("memory", {}):
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base_name = o.memory.base.get("prefix", "") + o.memory.base.name
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return {
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base_name: {
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"name": o.memory.base.get("prefix", "") + o.memory.base.name,
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"value": o.memory.post_indexed.value,
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}
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}
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return {}
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reg_operand_names = {} # e.g., {'rax': 'op1'}
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operand_state = {} # e.g., {'op1': {'name': 'rax', 'value': 0}} 0 means unchanged
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for o in instruction_form.operands:
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if "pre_indexed" in o.get("memory", {}):
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# Assuming no isa_data.operation
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if isa_data.get("operation", None) is not None:
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raise ValueError(
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"ISA information for pre-indexed instruction {!r} has operation set."
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"This is currently not supprted.".format(instruction_form.line)
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)
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base_name = o.memory.base.get("prefix", "") + o.memory.base.name
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reg_operand_names = {base_name: "op1"}
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operand_state = {"op1": {"name": base_name, "value": o.memory.offset.value}}
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if isa_data is not None and "operation" in isa_data:
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for i, o in enumerate(instruction_form.operands):
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operand_name = "op{}".format(i + 1)
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if "register" in o:
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o_reg_name = o["register"].get("prefix", "") + o["register"]["name"]
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reg_operand_names[o_reg_name] = operand_name
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operand_state[operand_name] = {"name": o_reg_name, "value": 0}
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elif "immediate" in o:
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operand_state[operand_name] = {"value": o["immediate"]["value"]}
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elif "memory" in o:
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# TODO lea needs some thinking about
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pass
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exec(isa_data["operation"], {}, operand_state)
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change_dict = {
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reg_name: operand_state.get(reg_operand_names.get(reg_name))
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for reg_name in dest_reg_names
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}
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return change_dict
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def _apply_found_ISA_data(self, isa_data, operands):
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"""
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Create operand dictionary containing src/dst operands out of the ISA data entry and
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the oeprands of an instruction form
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If breaks_pedendency_on_equal_operands is True (configuted per instruction in ISA db)
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and all operands are equal, place operand into destination only.
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:param dict isa_data: ISA DB entry
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:param list operands: operands of the instruction form
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:returns: `dict` -- operands dictionary with src/dst assignment
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"""
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op_dict = {}
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op_dict["source"] = []
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op_dict["destination"] = []
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op_dict["src_dst"] = []
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# handle dependency breaking instructions
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if "breaks_pedendency_on_equal_operands" in isa_data and operands[1:] == operands[:-1]:
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op_dict["destination"] += operands
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if "hidden_operands" in isa_data:
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op_dict["destination"] += [
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AttrDict.convert_dict(
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{hop["class"]: {k: hop[k] for k in ["class", "source", "destination"]}}
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)
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for hop in isa_data["hidden_operands"]
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]
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return op_dict
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for i, op in enumerate(isa_data["operands"]):
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if op["source"] and op["destination"]:
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op_dict["src_dst"].append(operands[i])
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continue
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if op["source"]:
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op_dict["source"].append(operands[i])
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continue
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if op["destination"]:
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op_dict["destination"].append(operands[i])
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continue
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# check for hidden operands like flags or registers
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if "hidden_operands" in isa_data:
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# add operand(s) to semantic_operands of instruction form
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for op in isa_data["hidden_operands"]:
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dict_key = (
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"src_dst"
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if op["source"] and op["destination"]
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else "source"
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if op["source"]
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else "destination"
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)
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hidden_op = {op["class"]: {}}
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key_filter = ["class", "source", "destination"]
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for key in [k for k in op.keys() if k not in key_filter]:
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hidden_op[op["class"]][key] = op[key]
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hidden_op = AttrDict.convert_dict(hidden_op)
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op_dict[dict_key].append(hidden_op)
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return op_dict
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def _has_load(self, instruction_form):
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"""Check if instruction form performs a LOAD"""
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for operand in chain(
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instruction_form["semantic_operands"]["source"],
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instruction_form["semantic_operands"]["src_dst"],
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):
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if "memory" in operand:
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return True
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return False
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def _has_store(self, instruction_form):
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"""Check if instruction form perfroms a STORE"""
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for operand in chain(
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instruction_form["semantic_operands"]["destination"],
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instruction_form["semantic_operands"]["src_dst"],
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):
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if "memory" in operand:
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return True
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return False
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def _get_regular_source_operands(self, instruction_form):
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"""Get source operand of given instruction form assuming regular src/dst behavior."""
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# if there is only one operand, assume it is a source operand
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if len(instruction_form["operands"]) == 1:
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return [instruction_form["operands"][0]]
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if self._isa == "x86":
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# return all but last operand
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return [op for op in instruction_form["operands"][0:-1]]
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elif self._isa == "aarch64":
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return [op for op in instruction_form["operands"][1:]]
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else:
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raise ValueError("Unsupported ISA {}.".format(self._isa))
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def _get_regular_destination_operands(self, instruction_form):
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"""Get destination operand of given instruction form assuming regular src/dst behavior."""
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# if there is only one operand, assume no destination
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if len(instruction_form["operands"]) == 1:
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return []
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if self._isa == "x86":
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# return last operand
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return instruction_form["operands"][-1:]
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if self._isa == "aarch64":
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# return first operand
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return instruction_form["operands"][:1]
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else:
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raise ValueError("Unsupported ISA {}.".format(self._isa))
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def substitute_mem_address(self, operands):
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"""Create memory wildcard for all memory operands"""
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return [self._create_reg_wildcard() if "memory" in op else op for op in operands]
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def _create_reg_wildcard(self):
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"""Wildcard constructor"""
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return {"*": "*"}
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