mirror of
https://github.com/RRZE-HPC/asmbench.git
synced 2025-07-21 04:31:05 +02:00
54 lines
1.4 KiB
Python
54 lines
1.4 KiB
Python
#!/usr/bin/env python3
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import ctypes
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import llvmlite.binding as llvm
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llvm.initialize()
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llvm.initialize_native_target()
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llvm.initialize_native_asmprinter()
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llvm.initialize_native_asmparser()
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code = """
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define i64 @"test"(i64 %"N")
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{
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entry:
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%"loop_cond" = icmp slt i64 0, %"N"
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br i1 %"loop_cond", label %"loop", label %"end"
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loop:
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%"loop_counter" = phi i64 [0, %"entry"], [%"loop_counter.1", %"loop"]
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%"in.0" = phi i32 [3, %"entry"], [%"out.0", %"loop"]
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%"reg.0" = call i32 asm "add $2, $0", "=r,0,i" (i32 %"in.0", i32 1)
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%"out.0" = call i32 asm "add $2, $0", "=r,0,i" (i32 %"reg.0", i32 1)
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%"loop_counter.1" = add i64 %"loop_counter", 1
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%"loop_cond.1" = icmp slt i64 %"loop_counter.1", %"N"
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br i1 %"loop_cond.1", label %"loop", label %"end"
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end:
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%"ret" = phi i64 [0, %"entry"], [%"loop_counter", %"loop"]
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ret i64 %"ret"
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}
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"""
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features = llvm.get_host_cpu_features().flatten()
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# znver1 on naples and skylake-avx512 on skylake-sp
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for cpu in ["skylake-avx512", "znver1"]:
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tm = llvm.Target.from_default_triple().create_target_machine(
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cpu=cpu, opt=2)
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tm.set_asm_verbosity(0)
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module = llvm.parse_assembly(code)
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asm = tm.emit_assembly(module)
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print(asm)
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with llvm.create_mcjit_compiler(module, tm) as ee:
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ee.finalize_object()
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cfptr = ee.get_function_address('test')
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cfunc = ctypes.CFUNCTYPE(ctypes.c_int64, ctypes.c_int64)(cfptr)
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print('->', cfunc(100000))
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