mirror of
https://github.com/RRZE-HPC/ibench.git
synced 2025-07-21 12:51:10 +02:00
moved benchmark creation from OSACA to ibench
This commit is contained in:
JanLJL
560
create_benchmarks.py
Executable file
560
create_benchmarks.py
Executable file
@@ -0,0 +1,560 @@
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#!/usr/bin/env python3
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import argparse
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import copy
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import os
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import sys
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from jinja2 import Template
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from osaca.parser import ParserAArch64v81, ParserX86ATT
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def main():
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parser = create_parser()
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args = parser.parse_args()
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asm_parser, input_str, output_path = check_arguments(args, parser)
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run(asm_parser, input_str, output_path)
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def create_parser():
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"""Return argparse parser."""
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# Create parser
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parser = argparse.ArgumentParser(
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description=(
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'Creates benchmark files for ibench out of AT&T x86 assembly '
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'or AArch64 ARM assembly code.'
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),
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epilog='For help, examples, documentation and bug reports go to:\nhttps://github.com'
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'/RRZE-HPC/ibench',
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)
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# Add arguments
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parser.add_argument(
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'ISA',
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type=str,
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help='Target instruction set of the code to parse. Currently either "x86" or "AArch64".',
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)
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group = parser.add_mutually_exclusive_group(required=True)
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group.add_argument(
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'-f',
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'--file',
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type=argparse.FileType('r'),
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help=(
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'Path to assembly file. All instructions will be parsed and creates '
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'ibench benchmarks for all of them.'
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),
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)
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group.add_argument(
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'-s',
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'--string',
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type=str,
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help=(
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'Example instruction string of instruction to '
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'create a benchmark for, e.g., "vmulsd %%xmm2, %%xmm1, %%xmm2".'
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),
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)
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parser.add_argument(
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'-o', '--output', type=str, help='Output directory for created benchmark files.'
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)
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return parser
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def check_arguments(args, parser):
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# Check ISA
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if args.ISA.lower() == 'x86':
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asm_parser = ParserX86ATT()
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elif args.ISA.lower() == 'aarch64':
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asm_parser = ParserAArch64v81()
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else:
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parser.error('Instruction set not suported. Please see --help for all valid options.')
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# Check input
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if args.string:
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input_str = args.string
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else:
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input_str = args.file.read()
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# Check output
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if args.output:
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output = args.output
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if not os.path.exists(args.output):
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os.makedirs(args.output)
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else:
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output = None
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return asm_parser, input_str, output
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def run(parser, code, output):
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parsed_code = parser.parse_file(code)
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ibench = IbenchAPI(parser.isa, benchmark_dir=output)
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pg = Progressbar(len(parsed_code))
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pg.start()
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for instruction_form in parsed_code:
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if instruction_form.instruction is not None and instruction_form.directive is None:
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ibench.create_ubenchmark(instruction_form)
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pg.increase(1)
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class IbenchAPI(object):
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def __init__(self, isa, benchmark_dir=None):
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self.isa = isa.lower()
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if not benchmark_dir:
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self.ibench_dir = os.path.dirname(os.path.abspath(__file__))
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else:
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assert os.path.exists(benchmark_dir)
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self.ibench_dir = benchmark_dir
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if not os.path.isdir(self.ibench_dir):
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os.makedirs(self.ibench_dir)
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def create_ubenchmark(self, instruction_form):
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if self.isa == 'aarch64':
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self.parser = ParserAArch64v81()
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tp_bench, lt_bench = self._create_ubench_aarch(instruction_form)
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elif self.isa == 'x86':
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self.parser = ParserX86ATT()
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tp_bench, lt_bench = self._create_ubench_x86(instruction_form)
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if tp_bench is None or lt_bench is None:
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return
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self._write_benchmark(self._get_ibench_name(instruction_form) + '-TP.S', tp_bench)
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self._write_benchmark(self._get_ibench_name(instruction_form) + '-LT.S', lt_bench)
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##########################################
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# HELPER FUNCTIONS
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##########################################
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def _write_benchmark(self, filename, content):
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with open(os.path.join(self.ibench_dir, filename), 'w') as f:
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f.write(content)
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def _get_ibench_name(self, instruction_form):
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name = ''
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op_sep = '_'
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name += instruction_form['instruction'].lower() + '-'
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operands = (
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instruction_form['operands']['operand_list']
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if 'operand_list' in instruction_form['operands']
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else instruction_form['operands']
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)
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if self.isa == 'aarch64':
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for op in operands:
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if 'register' in op:
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name += op['register']['prefix']
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name += op['register']['shape'] if 'shape' in op['register'] else ''
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elif 'immediate' in op:
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name += 'i'
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else:
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raise NotImplementedError
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name += op_sep
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elif self.isa == 'x86':
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for op in operands:
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if 'register' in op:
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name += (
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'r' if self.parser.is_gpr(op['register']) else op['register']['name'][0]
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)
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elif 'immediate' in op:
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name += 'i'
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name += op_sep
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else:
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raise NotImplementedError(
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'Currently only AArch64 and x86 architectures are supported.'
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)
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return name[:-1]
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def _create_ubench_aarch(self, instruction_form, num_instructions=8):
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loop_kernel_tp = ''
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loop_kernel_lt = ''
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vector_regs = False
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gp_regs = False
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mnemonic = instruction_form['instruction']
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operands = (
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instruction_form['operands']['operand_list']
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if 'operand_list' in instruction_form['operands']
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else instruction_form['operands']
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)
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for op in operands:
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if 'register' in op:
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if self.parser.is_gpr(op['register']):
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gp_regs = True
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elif self.parser.is_vector_register(op['register']):
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vector_regs = True
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elif 'memory' in op:
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return None, None
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elif 'identifier' in op:
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return None, None
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num_regs = len([x for x in operands if 'register' in x])
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# throughput benchmark
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possible_regs_tp = list(range(5, 16)) + list(range(19, 29))
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i = 0
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while i < num_instructions * num_regs:
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ops = []
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for op in operands:
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name = possible_regs_tp[i % len(possible_regs_tp)]
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ops.append(self._get_aarch_op(op, name))
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i += 1 if 'register' in op else 0
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line = '\tINSTR {}\n'.format(', '.join(ops))
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loop_kernel_tp += line
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# latency benchmark
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possible_regs_lt = list(range(5, 5 + num_regs))
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operands_lt = copy.deepcopy(operands)
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for i, x in enumerate(operands_lt):
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operands_lt[i] = (
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self._get_aarch_op(x, possible_regs_lt.pop())
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if 'register' in x
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else self._get_aarch_op(x, 0)
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)
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for i in range(0, 6):
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line = '\tINSTR {}\n'.format(', '.join(operands_lt))
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loop_kernel_lt += line
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operands_lt = self._invert_regs(operands, operands_lt)
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args_tp = {
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'instr': mnemonic,
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'ninst': num_instructions,
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'vector_regs': vector_regs,
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'gp_regs': gp_regs,
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'loop_kernel': loop_kernel_tp,
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}
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args_lt = {
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'instr': mnemonic,
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'ninst': 6,
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'vector_regs': vector_regs,
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'gp_regs': gp_regs,
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'loop_kernel': loop_kernel_lt,
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}
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return template_aarch64.render(**args_tp), template_aarch64.render(**args_lt)
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def _create_ubench_x86(self, instruction_form, num_instructions=8):
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loop_kernel_tp = ''
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loop_kernel_lt = ''
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gp_regs = False
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AVX = False
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AVX512 = False
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mnemonic = instruction_form['instruction']
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operands = list(
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reversed(
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copy.deepcopy(
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instruction_form['operands']['operand_list']
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if 'operand_list' in instruction_form['operands']
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else instruction_form['operands']
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)
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)
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)
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for op in operands:
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if 'register' in op:
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if self.parser.is_gpr(op['register']):
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gp_regs = True
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elif op['register']['name'][0].lower() == 'y':
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AVX = True
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elif op['register']['name'][0].lower() == 'z':
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AVX512 = True
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elif 'memory' in op:
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return None, None
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elif 'identifier' in op:
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return None, None
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num_regs = len([x for x in operands if 'register' in x])
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# throughput benchmark
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possible_regs_tp = {
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'gpr': ['ax', 'bx', 'cx', 'dx'] + list(range(9, 16)),
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'vector': list(range(0, 16)),
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}
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gpr_i = 0
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vector_i = 0
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for i in range(num_instructions):
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ops = []
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for op in operands:
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name = 0
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if 'register' in op:
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if self.parser.is_gpr(op['register']):
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name = possible_regs_tp['gpr'][gpr_i % len(possible_regs_tp['gpr'])]
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gpr_i += 1
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else:
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name = possible_regs_tp['vector'][
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vector_i % len(possible_regs_tp['vector'])
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]
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vector_i += 1
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ops.append(self._get_x86_op(op, name))
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line = '\tINSTR {}\n'.format(', '.join(ops))
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loop_kernel_tp += line
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# latency benchmark
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possible_regs_lt = list(range(9, 9 + num_regs))
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operands_lt = copy.deepcopy(operands)
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for i, x in enumerate(operands_lt):
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operands_lt[i] = (
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self._get_x86_op(x, possible_regs_lt.pop())
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if 'register' in x
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else self._get_x86_op(x, 0)
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)
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for i in range(0, 6):
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line = '\tINSTR {}\n'.format(', '.join(operands_lt))
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loop_kernel_lt += line
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operands_lt = self._invert_regs(operands, operands_lt)
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args_tp = {
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'instr': mnemonic,
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'ninst': num_instructions,
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'gp_regs': gp_regs,
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'AVX': AVX,
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'AVX512': AVX512,
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'loop_kernel': loop_kernel_tp.rstrip(),
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}
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args_lt = {
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'instr': mnemonic,
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'ninst': num_instructions,
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'gp_regs': gp_regs,
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'AVX': AVX,
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'AVX512': AVX512,
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'loop_kernel': loop_kernel_lt.rstrip(),
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}
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return template_x86.render(**args_tp), template_x86.render(**args_lt)
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def _get_aarch_op(self, operand, name):
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operand = copy.deepcopy(operand)
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if 'register' in operand:
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operand['register']['name'] = name
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return self.parser.get_full_reg_name(operand['register'])
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elif 'immediate' in operand:
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return '#192'
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else:
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raise NotImplementedError('Only immediates and register in benchmark allowed')
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def _get_x86_op(self, operand, name):
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operand = copy.deepcopy(operand)
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if 'register' in operand:
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reg_type = self.parser.get_reg_type(operand['register'])
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reg_type = reg_type[-1] if reg_type.startswith('gp') else reg_type
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operand['register']['name'] = reg_type + str(name)
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return self.parser.get_full_reg_name(operand['register'])
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elif 'immediate' in operand:
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return '192'
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else:
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raise NotImplementedError('Only immediates and register in benchmark allowed')
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def _invert_regs(self, operands, operand_str_list):
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reg_indices = [i for i, op in enumerate(operands) if 'register' in op]
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reg_indices_inverted = list(reversed(reg_indices))
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operands_tmp = [None for x in operand_str_list]
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for i in range(len(operand_str_list)):
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operands_tmp[i] = (
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operand_str_list[reg_indices_inverted[i]]
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if i in reg_indices
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else operand_str_list[i]
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)
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return operands_tmp
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class Progressbar(object):
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def __init__(self, width):
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self.line_width = 80
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self.width = width
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self.stepsize = self.line_width / width
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self.progress = 0
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self.line_progress = 0
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self.buffer = 0.0
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def start(self):
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self.progress = 1
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self.line_progress = 1
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sys.stdout.write('[%s]' % (' ' * self.line_width))
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sys.stdout.flush()
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# return to start of line, after '['
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sys.stdout.write('\b' * (self.line_width + 1))
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def increase(self, num=1):
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if self.progress == 0:
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self.start()
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if self.progress + num > self.width:
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for _ in range(self.line_width - self.line_progress + 1):
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sys.stdout.write('=')
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sys.stdout.flush()
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self.end()
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else:
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self.progress += num
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self.buffer += num * self.stepsize
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if self.buffer > 1.0:
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self.line_progress += int(self.buffer)
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sys.stdout.write('=' * int(self.buffer))
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sys.stdout.flush()
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self.buffer -= int(self.buffer)
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def end(self):
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self.progress = 0
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self.line_progress = 0
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sys.stdout.write(']\n')
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template_aarch64 = Template(
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'''#define INSTR {{ instr }}
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#define NINST {{ ninst }}
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#define N x0
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||||
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.globl ninst
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||||
.data
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||||
ninst:
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.long NINST
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.text
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||||
.globl latency
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.type latency, @function
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.align 32
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latency:
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{% if vector_regs %}
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||||
# push callee-save registers onto stack
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sub sp, sp, #64
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st1 {v8.4s, v9.4s, v10.4s, v11.4s}, [sp]
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sub sp, sp, #64
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st1 {v12.4s, v13.4s, v14.4s, v15.4s}, [sp]
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mov x4, N
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fmov v0.2d, #1.20000000
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fmov v1.2d, #1.23000000
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fmov v2.2d, #1.23400000
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fmov v3.2d, #1.23410000
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fmov v4.2d, #1.23412000
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fmov v5.2d, #1.23412300
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fmov v6.2d, #1.23412340
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fmov v7.2d, #1.23412341
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fmov v8.2d, #2.34123412
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||||
fmov v9.2d, #2.34123410
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||||
fmov v10.2d, #2.34123400
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fmov v11.2d, #2.34123000
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fmov v12.2d, #2.34120000
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fmov v13.2d, #2.34100000
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fmov v14.2d, #2.34000000
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fmov v15.2d, #2.30000000
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{% endif %}
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||||
{% if gp_regs %}
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||||
# push callee-save register onto stack
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push {x19-x28}
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||||
{% endif %}
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||||
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||||
loop:
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||||
subs x4, x4, #1
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||||
{{ loop_kernel }}
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||||
bne loop
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||||
done:
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||||
|
||||
{% if vector_regs %}
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||||
# pop callee-save registers from stack
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||||
ld1 {v12.4s, v13.4s, v14.4s, v15.4s}, [sp]
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||||
add sp, sp, #64
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||||
ld1 {v8.4s, v9.4s, v10.4s, v11.4s}, [sp]
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||||
add sp, sp, #64
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||||
{% endif %}
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||||
{% if gp_regs %}
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||||
pop {x19-x28}
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||||
{% endif %}
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||||
|
||||
ret
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||||
.size latency, .-latency
|
||||
'''
|
||||
)
|
||||
|
||||
template_x86 = Template(
|
||||
'''#define INSTR {{ instr }}
|
||||
#define NINST {{ ninst }}
|
||||
#define N edi
|
||||
#define i r8d
|
||||
|
||||
|
||||
.intel_syntax noprefix
|
||||
.globl ninst
|
||||
.data
|
||||
ninst:
|
||||
.long NINST
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||||
.text
|
||||
.globl latency
|
||||
.type latency, @function
|
||||
.align 32
|
||||
latency:
|
||||
push rbp
|
||||
mov rbp, rsp
|
||||
xor i, i
|
||||
test N, N
|
||||
jle done
|
||||
{% if gp_regs %}
|
||||
push rax
|
||||
push rbx
|
||||
push rcx
|
||||
push rdx
|
||||
push r9
|
||||
push r10
|
||||
push r11
|
||||
push r12
|
||||
push r13
|
||||
push r14
|
||||
push r15
|
||||
mov rax, 1
|
||||
mov rbx, 2
|
||||
mov rcx, 3
|
||||
mov rdx, 4
|
||||
mov r9, 5
|
||||
mov r10, 6
|
||||
mov r11, 7
|
||||
mov r12, 8
|
||||
mov r13, 9
|
||||
mov r14, 10
|
||||
mov r15, 11
|
||||
{% endif %}
|
||||
# create SP 1.0
|
||||
vpcmpeqw xmm0, xmm0, xmm0 # all ones
|
||||
vpslld xmm0, xmm0, 25 # logical left shift: 11111110..0 (25 = 32 - (8 - 1))
|
||||
vpsrld xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is 0
|
||||
{% if AVX or AVX512 %}
|
||||
# expand from SSE to AVX
|
||||
vinsertf128 ymm0, ymm0, xmm0, 0x1
|
||||
{% endif %}
|
||||
{% if AVX512 %}
|
||||
# expand from AVX to AVX-512
|
||||
vinsertf64x4 zmm0, zmm0, ymm0, 0x1
|
||||
{% endif %}
|
||||
{% if not AVX and not AVX512 %}
|
||||
# create SP 2.0
|
||||
vaddps xmm1, xmm0, xmm0
|
||||
# create SP 0.5
|
||||
vdivps xmm2, xmm0, xmm1
|
||||
{% endif %}
|
||||
{% if AVX and not AVX512 %}
|
||||
# create SP 2.0
|
||||
vaddps ymm1, ymm0, ymm0
|
||||
# create SP 0.5
|
||||
vdivps ymm2, ymm0, ymm1
|
||||
{% endif %}
|
||||
{% if AVX512 %}
|
||||
# create AVX-512 DP 2.0
|
||||
vaddps zmm1, zmm0, zmm0
|
||||
# create AVX-512 DP 0.5
|
||||
vdivps zmm2, zmm0, zmm1
|
||||
{% endif %}
|
||||
loop:
|
||||
inc i
|
||||
{{ loop_kernel }}
|
||||
cmp i, N
|
||||
jl loop
|
||||
done:
|
||||
{% if gp_regs %}
|
||||
pop r15
|
||||
pop r14
|
||||
pop r13
|
||||
pop r12
|
||||
pop r11
|
||||
pop r10
|
||||
pop r9
|
||||
pop rdx
|
||||
pop rcx
|
||||
pop rbx
|
||||
pop rax
|
||||
{% endif %}
|
||||
mov rsp, rbp
|
||||
pop rbp
|
||||
ret
|
||||
.size latency, .-latency
|
||||
'''
|
||||
)
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
Reference in New Issue
Block a user