The same MicroPython firmware is built for the HE but with slightly
different options, for example no USB.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
With this new Makefile you can build the following:
make BOARD=MY_BOARD MCU_CORE=M55_HP # build HP firmware/ToC.
make BOARD=MY_BOARD MCU_CORE=M55_HE # build HE firmware/ToC.
make BOARD=MY_BOARD MCU_CORE=M55_DUAL # build HE+HP firmware + ToC.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Includes services to get random numbers, reset SoC, get unique-id, dump SoC
info, and CPU control services.
Signed-off-by: Damien George <damien@micropython.org>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit adds the beginning of a new alif port with support for Alif
Ensemble MCUs. See https://alifsemi.com/
Supported features of this port added by this commit:
- UART REPL.
- TinyUSB support, for REPL and MSC.
- Octal SPI flash support, for filesystem.
- machine.Pin support.
General notes about the port:
- It uses make, similar to other bare-metal ports here.
- The toolchain is the standard arm-none-eabi- toolchain.
- Flashing a board can be done using either the built-in serial bootloader,
or JLink (both supported here).
- There are two required submodules (one for drivers/SDK, one for security
tools), both of which are open source and on GitHub.
- No special hardware or software is needed for development, just a board
connected over USB.
OpenMV have generously sponsored the development of this port.
Signed-off-by: Damien George <damien@micropython.org>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The cyw43-driver now provides the Bluetooth initialisation code, making
`drivers/cyw43/cywbt.c` obsolete. To use the new code a port must enable
the `CYW43_ENABLE_BLUETOOTH_OVER_UART` option.
Some ports have yet to migrate to the new code, so in the meantime they can
explicitly add the old source to their source list and continue to use it
without change.
Signed-off-by: Damien George <damien@micropython.org>
Configure flash timings dynamically to match the system clock. Reconfigure
timings after flash writes.
Changes are:
- ports/rp2/main.c: Set default flash timings.
- ports/rp2/modmachine.c: Configure optimal flash timings on freq change.
- ports/rp2/rp2_flash.c: Reconfigure flash when leaving critical section.
Signed-off-by: Phil Howard <github@gadgetoid.com>
Add a 256 byte (FLASH_PAGE_SIZE) SRAM copy buffer to allow copies from
PSRAM to flash. This would otherwise hardfault since PSRAM is disabled
when doing a write to flash.
Changes are:
- ports/rp2/rp2_flash.c: Add 256 byte (flash page size) SRAM copy buffer
for PSRAM to flash copies.
- ports/rp2/rp2_flash.c: Invalidate the XIP cache to purge any PSRAM
data before critical flash operations.
Co-authored-by: Phil Howard <github@gadgetoid.com>
Co-authored-by: Angus Gratton <angus@redyak.com.au>
Signed-off-by: Phil Howard <github@gadgetoid.com>
PSRAM will be used exclusively if MICROPY_GC_SPLIT_HEAP == 0, it will be
added to RAM if MICROPY_GC_SPLIT_HEAP == 1, and the system will fall back
to RAM only if it's not detected.
Due to the size of PSRAM, GC stack was overflowing and causing the GC to
scan through the entire memory pool. This caused noticable slowdowns
during GC. Increase the stack from 256 to 4096 bytes to avoid overflow and
increase the stack entry type size to accomodate 8MB+ PSRAM.
Changes are:
- ports/rp2/mpconfigport.h: Make split-heap optional and enable by default.
- ports/rp2/mpconfigport.h: Increase GC stack entry type to uint32_t.
- ports/rp2/mpconfigport.h: Raise GC stack size.
Co-authored-by: Kirk Benell <kirk.benell@sparkfun.com>
Signed-off-by: Phil Howard <github@gadgetoid.com>
Performs a best-effort attempt to detect attached PSRAM, configure it and
*add* it to the MicroPython heap. If PSRAM is not present, should fall
back to use internal RAM.
Introduce two new port/board defines:
- MICROPY_HW_ENABLE_PSRAM to enable PSRAM.
- MICROPY_HW_PSRAM_CS_PIN to define the chip-select pin (required).
Changes are:
- ports/rp2/rp2_psram.[ch]: Add new PSRAM module.
- ports/rp2/main.c: Add optional PSRAM support.
- ports/rp2/CMakeLists.txt: Include rp2_psram.c.
- ports/rp2/mpconfigport.h: Add MICROPY_HW_ENABLE_PSRAM.
- ports/rp2/modmachine.c: Reconfigure PSRAM on freq change.
Co-authored-by: Kirk Benell <kirk.benell@sparkfun.com>
Co-authored-by: Mike Bell <mike@mercuna.com>
Signed-off-by: Phil Howard <phil@gadgetoid.com>
This commit removes a definition used back when ESP-IDF v4 was supported
by MicroPython. Those times are now long gone, and so is the need for
that particular definition to be set in the first place.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit cleans up a couple of RISC-V specific directives in the
build script. Namely, removes the forced inclusion of the "riscv"
component and introduces proper mpy-cross flags.
The "riscv" component is already included by the ESP-IDF build
framework, as certain low-level components would not build otherwise, so
there is no need to add it to the required components list.
The architecture flag for mpy-cross is now set for RISC-V targets, as it
was previously set only for Xtensa targets (and it relied on a string
comparison rather than using the appropriate configuration variable).
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit changes the gchelper implementation in use for RV32-based
targets (ESP32C3, ESP32C6) from the generic one written in C to the one
written in assembler that is specific to the CPU in question.
The native implementation is already exercised on most CI builds as it
is used by the QEMU port to compile and test the RV32 target.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
The PYBD boards use an F7xx which has an errata 2.4.3:
Memory-mapped read operations may fail when timeout counter is enabled
This is unfortunate because it means that once QSPI memory-mapped flash is
accessed the QSPI peripheral will leave the CS pin active (low) forever,
which increases power consumption of the SPI flash chip (because it's
active and waiting for commands). The exact amount of power increase
depends on the flash, but the PYBD_SFx increase by about 2.5mA.
Previously this increase in power only happened when QSPI flash was needed,
eg on PYBD_SF2 when mbedtls or nimble libraries were used. On PYBD_SF6
it's actually never used.
But with the introduction of ROMFS which lives in the QSPI flash, the
memory is always access on start up to see if the ROMFS contains a valid
image (it must read the memory to find out). That means these boards
always consume about 2.5mA more after starting up (compared to when ROMFS
is disabled).
The fix in this commit is to explicitly restart the QSPI memory mapped mode
during the start up process. More precisely, the restart is done after
querying the ROMFS and just before trying to execute `boot.py`. That's the
right location to keep power consumption permanently down if the QSPI is
never used (eg ROMFS image doesn't exist).
Signed-off-by: Damien George <damien@micropython.org>
On stm32, the startup code attempts to mount the configured filesystem. If
there is an existing littlefs filesystem that's suitable corrupted it's
possible for the reported blocksize to be incorrect here:
uint32_t block_size = lfs2_fromle32(superblock->block_size);
This `block_size` (which is read from the filesystem iteself) is used to
create the len argument passed to `pyb_flash_make_new()`. In that function
the len arg is validated to be a mutliple of the underlying hardware block
size, as well as not bigger than the physical flash. Any failure is raised
as a ValueError. This exception is not caught currently in main, it flows
up to the high level assert / startup failure.
As this occurs before `boot.py` is run, the users (potentially frozen)
application code doesn't have any opportunity to detect and handle the
issue.
This commit adds a helper function which attempts to create a block device,
and on error returns `None` instead of raising an exception. Using this in
main means that a potentially corrupt filesystem will simply remain
unmounted, and the application can handle the issue safely.
The fix here also handles the case where the littlefs filesystem is valid
but the autodetection code (which detects the filesystem size) does not
work correctly. In that case it will retry mounting the filesystem using
the whole size of the block device.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
The rp2 port has an incomplete mDNS implementation. The code in `main.c`
calls `mdns_resp_init()` which opens the UDP socket for mDNS. However, no
code in the cyw43 driver makes the proper calls to `mdns_resp_add_netif()`
and `mdns_resp_remove_netif()` to send the announce packets. The wiznet5k
driver does make these calls and was used as a model for these changes.
This commit attempts to address this by very small changes to the
`ports/rp2/cyw43_configport.h` file. The change uses new cyw43 driver
hooks to map the driver macros `CYW43_CB_TCPIP_INIT_EXTRA` and
`CYW43_CB_TCPIP_DEINIT_EXTRA` to the appropriate lwIP mDNS calls.
Fixes issue #15297.
Signed-off-by: Mark Seminatore <nebula_peeps4t@icloud.com>
Rather than having Make calling CMake to generate a list of submodules and
then run a Make target (which is complex and prone to masking other
errors), implement the submodule update logic in CMake itself.
Internal CMake-side changes are that GIT_SUBMODULES is now a CMake list,
and the trigger variable name is changed from ECHO_SUBMODULES to
UPDATE_SUBMODULES.
The run is otherwise 100% a normal CMake run now, so most of the other
special casing can be removed.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
The buffer was be reset on every call to uart.init(). If no sizes were
given, the buffer was set to the default size 256. That made problems
e.g. with PPP.
This commit fixes it, keeping the buffer size if not deliberately changed
and allocating new buffers only if the size was changed. Cater for changes
of the bits value, which requires a change to the buffer size.
Signed-off-by: robert-hh <robert@hammelrath.com>
The buffer was be reset on every call to uart.init(). If no sizes were
given, the buffer was set to the default size 256. That made problems e.g.
with PPP.
This commit fixes it, keeping the buffer size if not deliberately changed
and allocating new buffers only if the size was changed.
Signed-off-by: robert-hh <robert@hammelrath.com>
Changes:
- Move setting of PendSV priority to pendsv_init().
- Call pendsv_init() from CPU1 as well, to ensure priority is the same.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
A better indication of whether a cyw43 event is pending is the actual flag
in the PendSV handler table. (If this fails, could also use the GPIO
interrupt enabled register bit).
This commit was needed of a previous version of the fix in the parent
commit, but it turned out not strictly necessary for the current version.
However, it's still a good clean up.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
There's a very odd but predictable sequence of events that breaks Wi-Fi
when using both cores:
1) CPU1 calls pendsv_suspend() - for example sleep() causes
a softtimer node to be inserted, which calls pendsv_suspend().
2) CYW43 sends wakeup IRQ. CPU0 GPIO IRQ handler schedules PendSV
and disables the GPIO IRQ on CPU0, to re-enable after
cyw43_poll() runs and completes.
3) CPU0 PendSV_Handler runs, sees pendsv is suspended, exits.
4) CPU1 calls pendsv_resume() and pendsv_resume() sees PendSV
is pending and triggers it on CPU1.
5) CPU1 runs PendSV_Handler, runs cyw43_poll(), and at the end
it re-enables the IRQ *but now on CPU1*.
However CPU1 has GPIO IRQs disabled, so the CYW43 interrupt never runs
again...
The fix in this commit is to always enable/disable the interrupt on CPU0.
This isn't supported by the pico-sdk, but it is supported by the hardware.
Fixes issue #16779.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
It's common with write-only SPI displays for MISO to be repurposed as a
register select or data/command pin.
While that was possible by setting up the pin after a call to
`machine.SPI()` this change makes `machine.SPI(miso=None)` explicit.
Signed-off-by: Phil Howard <github@gadgetoid.com>
If the "spi_id" arg is not supplied and then the board default specified by
PICO_DEFAULT_SPI will be used.
Signed-off-by: Phil Howard <github@gadgetoid.com>
When PICO_DEFAULT_I2C is not set require an I2C bus ID instead of
using -1 as a default, which would fail with a cryptic:
"I2C(-1) doesn't exist"
Signed-off-by: Phil Howard <github@gadgetoid.com>
