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https://github.com/micropython/micropython.git
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This commit adds support for writing inline assembler functions when targeting a RV32IMC processor. Given that this takes up a bit of rodata space due to its large instruction decoding table and its extensive error messages, it is enabled by default only on offline targets such as mpy-cross and the qemu port. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
163 lines
1.5 KiB
Plaintext
163 lines
1.5 KiB
Plaintext
- slli
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+ slli
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- srli
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+ srli
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- srai
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+ srai
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- c_slli
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+ c_slli
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- c_srli
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+ c_srli
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- c_srai
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+ c_srai
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0 c_slli
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0 c_slli
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zero c_srli
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s2 c_srli
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s3 c_srli
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s4 c_srli
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s5 c_srli
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s6 c_srli
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s7 c_srli
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s8 c_srli
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s9 c_srli
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s10 c_srli
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s11 c_srli
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a6 c_srli
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a7 c_srli
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tp c_srli
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gp c_srli
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sp c_srli
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ra c_srli
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t0 c_srli
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t1 c_srli
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t2 c_srli
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t3 c_srli
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t4 c_srli
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t5 c_srli
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t6 c_srli
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x0 c_srli
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x1 c_srli
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x2 c_srli
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x3 c_srli
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x4 c_srli
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x5 c_srli
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x6 c_srli
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x7 c_srli
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x16 c_srli
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x17 c_srli
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x18 c_srli
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x19 c_srli
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x20 c_srli
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x21 c_srli
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x22 c_srli
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x23 c_srli
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x24 c_srli
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x25 c_srli
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x26 c_srli
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x27 c_srli
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x28 c_srli
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x29 c_srli
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x30 c_srli
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x31 c_srli
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zero c_srai
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s2 c_srai
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s3 c_srai
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s4 c_srai
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s5 c_srai
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s6 c_srai
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s7 c_srai
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s8 c_srai
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s9 c_srai
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s10 c_srai
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s11 c_srai
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a6 c_srai
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a7 c_srai
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tp c_srai
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gp c_srai
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sp c_srai
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ra c_srai
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t0 c_srai
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t1 c_srai
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t2 c_srai
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t3 c_srai
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t4 c_srai
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t5 c_srai
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t6 c_srai
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x0 c_srai
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x1 c_srai
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x2 c_srai
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x3 c_srai
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x4 c_srai
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x5 c_srai
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x6 c_srai
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x7 c_srai
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x16 c_srai
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x17 c_srai
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x18 c_srai
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x19 c_srai
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x20 c_srai
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x21 c_srai
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x22 c_srai
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x23 c_srai
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x24 c_srai
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x25 c_srai
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x26 c_srai
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x27 c_srai
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x28 c_srai
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x29 c_srai
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x30 c_srai
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x31 c_srai
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0l c_mv
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0r c_mv
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0b c_mv
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0l c_add
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0r c_add
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0b c_add
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0 c_jr
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>s addi
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<s addi
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>s andi
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<s andi
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>s ori
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<s ori
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>s slti
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<s slti
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>s sltiu
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<s sltiu
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>s xori
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<s xori
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>s lb
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<s lb
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>s lbu
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<s lbu
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>s lh
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<s lh
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>s lhu
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<s lhu
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>s lw
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<s lw
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>s sb
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<s sb
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>s sh
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<s sh
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>s sw
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<s sw
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00 c_addi
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>0 c_addi
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<0 c_addi
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<s c_addi
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>s c_addi
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00 c_andi
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>0 c_andi
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<0 c_andi
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<s c_andi
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>s c_andi
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c_and
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c_or
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c_xor
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>s c_lw
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<s c_lw
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>s c_sw
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<s c_sw
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