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Scenario: module1 depends on some common file from lib/, so specifies it in its SRC_MOD, and the same situation with module2, then common file from lib/ eventually ends up listed twice in $(OBJ), which leads to link errors. Make is equipped to deal with such situation easily, quoting the manual: "The value of $^ omits duplicate prerequisites, while $+ retains them and preserves their order." So, just use $^ consistently in all link targets.