mirror of
https://github.com/micropython/micropython.git
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132 lines
4.9 KiB
C
132 lines
4.9 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024-2025 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mphal.h"
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#include "boardctrl.h"
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#include "xspi.h"
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// Values for OTP fuses for VDDIO2/3, to select low voltage mode (<2.5V).
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// See RM0486, Section 5, Table 18.
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#define BSEC_HW_CONFIG_ID (124U)
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#define BSEC_HWS_HSLV_VDDIO3 (1U << 15)
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#define BSEC_HWS_HSLV_VDDIO2 (1U << 16)
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#define OMV_BOOT_MAGIC_ADDR (0x3401FFFCU)
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#define OMV_BOOT_MAGIC_VALUE (0xB00710ADU)
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void mboot_board_early_init(void) {
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// TODO: move some of the below code to a common location for all N6 boards?
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// Enable PWR, BSEC and SYSCFG clocks.
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
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LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
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LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
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// Program high speed IO optimization fuses if they aren't already set.
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uint32_t fuse;
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BSEC_HandleTypeDef hbsec = { .Instance = BSEC };
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const uint32_t mask = BSEC_HWS_HSLV_VDDIO2 | BSEC_HWS_HSLV_VDDIO3;
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if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
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fuse = 0;
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} else if ((fuse & mask) != mask) {
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// Program the fuse, and read back the set value.
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if (HAL_BSEC_OTP_Program(&hbsec, BSEC_HW_CONFIG_ID, fuse | mask, HAL_BSEC_NORMAL_PROG) != HAL_OK) {
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fuse = 0;
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} else if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
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fuse = 0;
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}
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}
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// Enable Vdd ADC, needed for the ADC to work.
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LL_PWR_EnableVddADC();
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// Configure VDDIO2. Only enable 1.8V mode if the fuse is set.
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LL_PWR_EnableVddIO2();
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if (fuse & BSEC_HWS_HSLV_VDDIO2) {
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LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
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}
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SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
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// Configure VDDIO3. Only enable 1.8V mode if the fuse is set.
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LL_PWR_EnableVddIO3();
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if (fuse & BSEC_HWS_HSLV_VDDIO3) {
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LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
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}
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SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
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// Configure VDDIO4.
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LL_PWR_EnableVddIO4();
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LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
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SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
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// Enable VDD for ADC and USB.
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LL_PWR_EnableVddADC();
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LL_PWR_EnableVddUSB();
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// Enable XSPI in memory-mapped mode.
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xspi_init();
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}
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void board_enter_bootloader(unsigned int n_args, const void *args) {
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// Support both OpenMV bootloader and mboot.
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*((uint32_t *)OMV_BOOT_MAGIC_ADDR) = OMV_BOOT_MAGIC_VALUE;
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SCB_CleanDCache();
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boardctrl_maybe_enter_mboot(n_args, args);
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}
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void board_early_init(void) {
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// TODO: if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY ) != HAL_OK)
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LL_PWR_EnableWakeUpPin(LL_PWR_WAKEUP_PIN3 | LL_PWR_WAKEUP_PIN2);
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LL_PWR_SetWakeUpPinPolarityLow(LL_PWR_WAKEUP_PIN3 | LL_PWR_WAKEUP_PIN2);
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}
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void board_leave_standby(void) {
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// TODO: move some of the below code to a common location for all N6 boards?
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// Enable PWR, BSEC and SYSCFG clocks.
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
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LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
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LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
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// Configure VDDIO2 (1.8V mode selection is retained).
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LL_PWR_EnableVddIO2();
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SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
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// Configure VDDIO3 (1.8V mode selection is retained).
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LL_PWR_EnableVddIO3();
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SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
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// Configure VDDIO4.
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LL_PWR_EnableVddIO4();
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LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
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SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
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// Enable VDD for ADC and USB.
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LL_PWR_EnableVddADC();
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LL_PWR_EnableVddUSB();
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}
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