mirror of
https://github.com/micropython/micropython.git
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268acb714d
This commit adds support for writing inline assembler functions when targeting a RV32IMC processor. Given that this takes up a bit of rodata space due to its large instruction decoding table and its extensive error messages, it is enabled by default only on offline targets such as mpy-cross and the qemu port. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
80 lines
1.1 KiB
Python
80 lines
1.1 KiB
Python
# test arithmetic opcodes
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@micropython.asm_rv32
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def f1():
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li(a0, 0x100)
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li(a1, 1)
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add(a0, a0, a1)
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addi(a0, a0, 1)
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addi(a0, a0, -2)
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sub(a0, a0, a1)
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c_add(a0, a1)
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c_addi(a0, -1)
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c_sub(a0, a1)
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print(hex(f1()))
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@micropython.asm_rv32
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def f2():
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li(a0, 0x10FF)
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li(a1, 1)
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and_(a2, a0, a1)
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andi(a3, a0, 0x10)
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or_(a2, a2, a3)
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ori(a2, a2, 8)
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li(a1, 0x200)
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c_or(a2, a1)
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li(a1, 0xF0)
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mv(a0, a2)
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c_and(a0, a1)
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li(a1, 0x101)
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xor(a0, a0, a1)
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xori(a0, a0, 0x101)
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c_xor(a0, a1)
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print(hex(f2()))
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@micropython.asm_rv32
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def f3(a0, a1):
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slt(a0, a0, a1)
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print(f3(0xFFFFFFF0, 0xFFFFFFF1))
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print(f3(0x0, 0xFFFFFFF1))
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print(f3(0xFFFFFFF1, 0xFFFFFFF1))
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print(f3(0xFFFFFFF1, 0xFFFFFFF0))
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@micropython.asm_rv32
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def f4(a0, a1):
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sltu(a0, a0, a1)
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print(f3(0xFFFFFFF0, 0xFFFFFFF1))
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print(f3(0x0, 0xFFFFFFF1))
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print(f3(0xFFFFFFF1, 0xFFFFFFF1))
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print(f3(0xFFFFFFF1, 0xFFFFFFF0))
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@micropython.asm_rv32
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def f5(a0):
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slti(a0, a0, -2)
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print(f5(-1))
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print(f5(-3))
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@micropython.asm_rv32
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def f6(a0):
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sltiu(a0, a0, -2)
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print(f6(-1))
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print(f6(-3))
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