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https://github.com/micropython/micropython.git
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268acb714d
This commit adds support for writing inline assembler functions when targeting a RV32IMC processor. Given that this takes up a bit of rodata space due to its large instruction decoding table and its extensive error messages, it is enabled by default only on offline targets such as mpy-cross and the qemu port. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
87 lines
1.4 KiB
Python
87 lines
1.4 KiB
Python
# test load/store opcodes
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@micropython.asm_rv32
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def l():
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li(a5, 4)
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addi(sp, sp, -12)
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li(a0, 0x123)
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c_swsp(a0, 0)
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addi(a1, a0, 0x111)
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c_swsp(a1, 4)
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addi(a2, a1, 0x111)
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c_swsp(a2, 8)
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mv(a4, sp)
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c_lw(a3, 0(a4))
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bne(a3, a0, END)
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addi(a5, a5, -1)
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lw(a3, 4(a4))
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bne(a3, a1, END)
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addi(a5, a5, -1)
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lhu(a3, 8(a4))
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bne(a3, a2, END)
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addi(a5, a5, -1)
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lbu(a0, 8(a4))
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addi(a0, a0, 0x300)
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bne(a0, a2, END)
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addi(a5, a5, -1)
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label(END)
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addi(sp, sp, 12)
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mv(a0, a5)
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print(l())
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@micropython.asm_rv32
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def s():
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li(a5, 4)
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addi(sp, sp, -12)
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c_swsp(zero, 0)
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c_swsp(zero, 4)
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c_swsp(zero, 8)
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li(a0, 0x12345)
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mv(a4, sp)
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c_sw(a0, 0(a4))
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sh(a0, 4(a4))
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sb(a0, 8(a4))
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li(a1, 0xFFFF)
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and_(a1, a0, a1)
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andi(a2, a0, 0xFF)
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lw(a3, 0(sp))
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bne(a3, a0, END)
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addi(a5, a5, -1)
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lw(a3, 4(sp))
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bne(a3, a1, END)
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addi(a5, a5, -1)
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lw(a3, 8(sp))
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bne(a3, a2, END)
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addi(a5, a5, -1)
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label(END)
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addi(sp, sp, 12)
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mv(a0, a5)
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print(s())
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@micropython.asm_rv32
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def lu():
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li(a5, 4)
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addi(sp, sp, -8)
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li(a0, 0xF1234567)
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c_swsp(a0, 0)
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c_swsp(a0, 4)
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lh(a1, 0(sp))
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blt(a1, zero, END)
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addi(a5, a5, -1)
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lb(a2, 4(sp))
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blt(a2, zero, END)
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addi(a5, a5, -1)
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label(END)
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addi(sp, sp, 8)
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mv(a0, a5)
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print(lu())
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