mirror of
https://github.com/andreas-abel/nanoBench.git
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291 lines
8.6 KiB
Plaintext
291 lines
8.6 KiB
Plaintext
# Based on https://download.01.org/perfmon/GLP/goldmontplus_core_v1.01.json
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# Applies to processors with family-model in {6-7A}
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# Loads blocked due to store data not ready (Precise event capable)
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03.01 LD_BLOCKS.DATA_UNKNOWN
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# Loads blocked due to store forward restriction (Precise event capable)
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03.02 LD_BLOCKS.STORE_FORWARD
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# Loads blocked because address has 4k partial address false dependence (Precise event capable)
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03.04 LD_BLOCKS.4K_ALIAS
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# Loads blocked because address in not in the UTLB (Precise event capable)
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03.08 LD_BLOCKS.UTLB_MISS
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# Loads blocked (Precise event capable)
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03.10 LD_BLOCKS.ALL_BLOCK
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# Page walk completed due to a demand load to a 4K page
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08.02 DTLB_LOAD_MISSES.WALK_COMPLETED_4K
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# Page walk completed due to a demand load to a 2M or 4M page
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08.04 DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M
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# Page walk completed due to a demand load to a 1GB page
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08.08 DTLB_LOAD_MISSES.WALK_COMPLETED_1GB
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# Page walks outstanding due to a demand load every cycle.
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08.10 DTLB_LOAD_MISSES.WALK_PENDING
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# Uops issued to the back end per cycle
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0E.00 UOPS_ISSUED.ANY
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# Load uops that split a page (Precise event capable)
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13.02 MISALIGN_MEM_REF.LOAD_PAGE_SPLIT
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# Store uops that split a page (Precise event capable)
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13.04 MISALIGN_MEM_REF.STORE_PAGE_SPLIT
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# L2 cache request misses
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2E.41 LONGEST_LAT_CACHE.MISS
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# L2 cache requests
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2E.4F LONGEST_LAT_CACHE.REFERENCE
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# Requests rejected by the XQ
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30.00 L2_REJECT_XQ.ALL
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# Requests rejected by the L2Q
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31.00 CORE_REJECT_L2Q.ALL
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# Core cycles when core is not halted
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3C.00 CPU_CLK_UNHALTED.CORE_P
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# Reference cycles when core is not halted
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3C.01 CPU_CLK_UNHALTED.REF
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# Page walk completed due to a demand data store to a 4K page
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49.02 DTLB_STORE_MISSES.WALK_COMPLETED_4K
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# Page walk completed due to a demand data store to a 2M or 4M page
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49.04 DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
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# Page walk completed due to a demand data store to a 1GB page
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49.08 DTLB_STORE_MISSES.WALK_COMPLETED_1GB
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# Page walks outstanding due to a demand data store every cycle.
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49.10 DTLB_STORE_MISSES.WALK_PENDING
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# Page walks outstanding due to walking the EPT every cycle
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4F.10 EPT.WALK_PENDING
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# L1 Cache evictions for dirty data
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51.01 DL1.REPLACEMENT
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# References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture
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80.01 ICACHE.HIT
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# References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture
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80.02 ICACHE.MISSES
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# References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture
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80.03 ICACHE.ACCESSES
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# ITLB misses
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81.04 ITLB.MISS
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# Page walk completed due to an instruction fetch in a 4K page
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85.02 ITLB_MISSES.WALK_COMPLETED_4K
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# Page walk completed due to an instruction fetch in a 2M or 4M page
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85.04 ITLB_MISSES.WALK_COMPLETED_2M_4M
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# Page walk completed due to an instruction fetch in a 1GB page
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85.08 ITLB_MISSES.WALK_COMPLETED_1GB
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# Page walks outstanding due to an instruction fetch every cycle.
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85.10 ITLB_MISSES.WALK_PENDING
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# Cycles code-fetch stalled due to any reason.
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86.00 FETCH_STALL.ALL
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# Cycles the code-fetch stalls and an ITLB miss is outstanding.
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86.01 FETCH_STALL.ITLB_FILL_PENDING_CYCLES
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# Cycles code-fetch stalled due to an outstanding ICache miss.
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86.02 FETCH_STALL.ICACHE_FILL_PENDING_CYCLES
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# Uops requested but not-delivered to the back-end per cycle
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9C.00 UOPS_NOT_DELIVERED.ANY
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# STLB flushes
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BD.20 TLB_FLUSHES.STLB_ANY
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# Instructions retired (Precise event capable)
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C0.00 INST_RETIRED.ANY_P
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# Instructions retired - using Reduced Skid PEBS feature
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C0.00 INST_RETIRED.PREC_DIST
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# Uops retired (Precise event capable)
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C2.00 UOPS_RETIRED.ANY
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# MS uops retired (Precise event capable)
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C2.01 UOPS_RETIRED.MS
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# Floating point divide uops retired (Precise Event Capable)
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C2.08 UOPS_RETIRED.FPDIV
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# Integer divide uops retired (Precise Event Capable)
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C2.10 UOPS_RETIRED.IDIV
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# All machine clears
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C3.00 MACHINE_CLEARS.ALL
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# Self-Modifying Code detected
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C3.01 MACHINE_CLEARS.SMC
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# Machine clears due to memory ordering issue
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C3.02 MACHINE_CLEARS.MEMORY_ORDERING
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# Machine clears due to FP assists
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C3.04 MACHINE_CLEARS.FP_ASSIST
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# Machine clears due to memory disambiguation
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C3.08 MACHINE_CLEARS.DISAMBIGUATION
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# Machines clear due to a page fault
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C3.20 MACHINE_CLEARS.PAGE_FAULT
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# Retired branch instructions (Precise event capable)
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C4.00 BR_INST_RETIRED.ALL_BRANCHES
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# Retired conditional branch instructions (Precise event capable)
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C4.7E BR_INST_RETIRED.JCC
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# Retired taken branch instructions (Precise event capable)
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C4.80 BR_INST_RETIRED.ALL_TAKEN_BRANCHES
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# Retired far branch instructions (Precise event capable)
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C4.BF BR_INST_RETIRED.FAR_BRANCH
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# Retired instructions of near indirect Jmp or call (Precise event capable)
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C4.EB BR_INST_RETIRED.NON_RETURN_IND
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# Retired near return instructions (Precise event capable)
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C4.F7 BR_INST_RETIRED.RETURN
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# Retired near call instructions (Precise event capable)
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C4.F9 BR_INST_RETIRED.CALL
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# Retired near indirect call instructions (Precise event capable)
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C4.FB BR_INST_RETIRED.IND_CALL
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# Retired near relative call instructions (Precise event capable)
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C4.FD BR_INST_RETIRED.REL_CALL
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# Retired conditional branch instructions that were taken (Precise event capable)
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C4.FE BR_INST_RETIRED.TAKEN_JCC
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# Retired mispredicted branch instructions (Precise event capable)
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C5.00 BR_MISP_RETIRED.ALL_BRANCHES
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# Retired mispredicted conditional branch instructions (Precise event capable)
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C5.7E BR_MISP_RETIRED.JCC
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# Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable)
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C5.EB BR_MISP_RETIRED.NON_RETURN_IND
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# Retired mispredicted near return instructions (Precise event capable)
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C5.F7 BR_MISP_RETIRED.RETURN
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# Retired mispredicted near indirect call instructions (Precise event capable)
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C5.FB BR_MISP_RETIRED.IND_CALL
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# Retired mispredicted conditional branch instructions that were taken (Precise event capable)
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C5.FE BR_MISP_RETIRED.TAKEN_JCC
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# Unfilled issue slots per cycle
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CA.00 ISSUE_SLOTS_NOT_CONSUMED.ANY
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# Unfilled issue slots per cycle because of a full resource in the backend
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CA.01 ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL
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# Unfilled issue slots per cycle to recover
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CA.02 ISSUE_SLOTS_NOT_CONSUMED.RECOVERY
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# Hardware interrupts received
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CB.01 HW_INTERRUPTS.RECEIVED
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# Cycles hardware interrupts are masked
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CB.02 HW_INTERRUPTS.MASKED
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# Cycles pending interrupts are masked
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CB.04 HW_INTERRUPTS.PENDING_AND_MASKED
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# Cycles a divider is busy
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CD.00 CYCLES_DIV_BUSY.ALL
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# Cycles the integer divide unit is busy
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CD.01 CYCLES_DIV_BUSY.IDIV
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# Cycles the FP divide unit is busy
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CD.02 CYCLES_DIV_BUSY.FPDIV
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# Load uops retired that missed the DTLB (Precise event capable)
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D0.11 MEM_UOPS_RETIRED.DTLB_MISS_LOADS
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# Store uops retired that missed the DTLB (Precise event capable)
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D0.12 MEM_UOPS_RETIRED.DTLB_MISS_STORES
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# Memory uops retired that missed the DTLB (Precise event capable)
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D0.13 MEM_UOPS_RETIRED.DTLB_MISS
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# Locked load uops retired (Precise event capable)
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D0.21 MEM_UOPS_RETIRED.LOCK_LOADS
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# Load uops retired that split a cache-line (Precise event capable)
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D0.41 MEM_UOPS_RETIRED.SPLIT_LOADS
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# Stores uops retired that split a cache-line (Precise event capable)
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D0.42 MEM_UOPS_RETIRED.SPLIT_STORES
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# Memory uops retired that split a cache-line (Precise event capable)
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D0.43 MEM_UOPS_RETIRED.SPLIT
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# Load uops retired (Precise event capable)
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D0.81 MEM_UOPS_RETIRED.ALL_LOADS
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# Store uops retired (Precise event capable)
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D0.82 MEM_UOPS_RETIRED.ALL_STORES
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# Memory uops retired (Precise event capable)
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D0.83 MEM_UOPS_RETIRED.ALL
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# Load uops retired that hit L1 data cache (Precise event capable)
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D1.01 MEM_LOAD_UOPS_RETIRED.L1_HIT
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# Load uops retired that hit L2 (Precise event capable)
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D1.02 MEM_LOAD_UOPS_RETIRED.L2_HIT
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# Load uops retired that missed L1 data cache (Precise event capable)
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D1.08 MEM_LOAD_UOPS_RETIRED.L1_MISS
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# Load uops retired that missed L2 (Precise event capable)
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D1.10 MEM_LOAD_UOPS_RETIRED.L2_MISS
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# Memory uop retired where cross core or cross module HITM occurred (Precise event capable)
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D1.20 MEM_LOAD_UOPS_RETIRED.HITM
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# Loads retired that hit WCB (Precise event capable)
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D1.40 MEM_LOAD_UOPS_RETIRED.WCB_HIT
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# Loads retired that came from DRAM (Precise event capable)
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D1.80 MEM_LOAD_UOPS_RETIRED.DRAM_HIT
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# BACLEARs asserted for any branch type
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E6.01 BACLEARS.ALL
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# BACLEARs asserted for return branch
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E6.08 BACLEARS.RETURN
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# BACLEARs asserted for conditional branch
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E6.10 BACLEARS.COND
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# MS decode starts
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E7.01 MS_DECODED.MS_ENTRY
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# Decode restrictions due to predicting wrong instruction length
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E9.01 DECODE_RESTRICTION.PREDECODE_WRONG
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