nanoBench/configs/cfg_SandyBridge_all_core.txt

# Based on https://download.01.org/perfmon/SNB/sandybridge_core_v16.json
# Applies to processors with family-model in {6-2A}

# Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.
03.01 LD_BLOCKS.DATA_UNKNOWN

# Cases when loads get true Block-on-Store blocking code preventing store forwarding.
03.02 LD_BLOCKS.STORE_FORWARD

# This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
03.08 LD_BLOCKS.NO_SR

# Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).
03.10 LD_BLOCKS.ALL_BLOCK

# Speculative cache line split load uops dispatched to L1 cache.
05.01 MISALIGN_MEM_REF.LOADS

# Speculative cache line split STA uops dispatched to L1 cache.
05.02 MISALIGN_MEM_REF.STORES

# False dependencies in MOB due to partial compare.
07.01 LD_BLOCKS_PARTIAL.ADDRESS_ALIAS

# This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.
07.08 LD_BLOCKS_PARTIAL.ALL_STA_BLOCK

# Load misses in all DTLB levels that cause page walks.
08.01 DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK

# Load misses at all DTLB levels that cause completed page walks.
08.02 DTLB_LOAD_MISSES.WALK_COMPLETED

# Cycles when PMH is busy with page walks.
08.04 DTLB_LOAD_MISSES.WALK_DURATION

# Load operations that miss the first DTLB level but hit the second and do not cause page walks.
08.10 DTLB_LOAD_MISSES.STLB_HIT

# Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).
0D.03.CMSK=1 INT_MISC.RECOVERY_CYCLES

# Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).
0D.03.CMSK=1.AnyT INT_MISC.RECOVERY_CYCLES_ANY

# Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).
0D.03.CMSK=1.EDG INT_MISC.RECOVERY_STALLS_COUNT

# Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.
0D.40 INT_MISC.RAT_STALL_CYCLES

# Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).
0E.01 UOPS_ISSUED.ANY

# Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.
0E.01.CMSK=1.AnyT.INV UOPS_ISSUED.CORE_STALL_CYCLES

# Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.
0E.01.CMSK=1.INV UOPS_ISSUED.STALL_CYCLES

# Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.
10.01 FP_COMP_OPS_EXE.X87

# Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.
10.10 FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE

# Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.
10.20 FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE

# Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.
10.40 FP_COMP_OPS_EXE.SSE_PACKED_SINGLE

# Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.
10.80 FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE

# Number of GSSE-256 Computational FP single precision uops issued this cycle.
11.01 SIMD_FP_256.PACKED_SINGLE

# Number of AVX-256 Computational FP double precision uops issued this cycle.
11.02 SIMD_FP_256.PACKED_DOUBLE

# Cycles when divider is busy executing divide operations.
14.01 ARITH.FPU_DIV_ACTIVE

# Divide operations executed.
14.01.CMSK=1.EDG ARITH.FPU_DIV

# Valid instructions written to IQ per cycle.
17.01 INSTS_WRITTEN_TO_IQ.INSTS

# Demand Data Read requests that hit L2 cache.
24.01 L2_RQSTS.DEMAND_DATA_RD_HIT

# Demand Data Read requests.
24.03 L2_RQSTS.ALL_DEMAND_DATA_RD

# RFO requests that hit L2 cache.
24.04 L2_RQSTS.RFO_HIT

# RFO requests that miss L2 cache.
24.08 L2_RQSTS.RFO_MISS

# RFO requests to L2 cache.
24.0C L2_RQSTS.ALL_RFO

# L2 cache hits when fetching instructions, code reads.
24.10 L2_RQSTS.CODE_RD_HIT

# L2 cache misses when fetching instructions.
24.20 L2_RQSTS.CODE_RD_MISS

# L2 code requests.
24.30 L2_RQSTS.ALL_CODE_RD

# Requests from the L2 hardware prefetchers that hit L2 cache.
24.40 L2_RQSTS.PF_HIT

# Requests from the L2 hardware prefetchers that miss L2 cache.
24.80 L2_RQSTS.PF_MISS

# Requests from L2 hardware prefetchers.
24.C0 L2_RQSTS.ALL_PF

# RFOs that miss cache lines.
27.01 L2_STORE_LOCK_RQSTS.MISS

# RFOs that hit cache lines in E state.
27.04 L2_STORE_LOCK_RQSTS.HIT_E

# RFOs that hit cache lines in M state.
27.08 L2_STORE_LOCK_RQSTS.HIT_M

# RFOs that access cache lines in any state.
27.0F L2_STORE_LOCK_RQSTS.ALL

# Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).
28.01 L2_L1D_WB_RQSTS.MISS

# Not rejected writebacks from L1D to L2 cache lines in S state.
28.02 L2_L1D_WB_RQSTS.HIT_S

# Not rejected writebacks from L1D to L2 cache lines in E state.
28.04 L2_L1D_WB_RQSTS.HIT_E

# Not rejected writebacks from L1D to L2 cache lines in M state.
28.08 L2_L1D_WB_RQSTS.HIT_M

# Not rejected writebacks from L1D to L2 cache lines in any state.
28.0F L2_L1D_WB_RQSTS.ALL

# Core-originated cacheable demand requests missed LLC.
2E.41 LONGEST_LAT_CACHE.MISS

# Core-originated cacheable demand requests that refer to LLC.
2E.4F LONGEST_LAT_CACHE.REFERENCE

# Thread cycles when thread is not in halt state.
3C.00 CPU_CLK_UNHALTED.THREAD_P

# Core cycles when at least one thread on the physical core is not in halt state.
3C.00.AnyT CPU_CLK_UNHALTED.THREAD_P_ANY

# Reference cycles when the thread is unhalted (counts at 100 MHz rate).
3C.01 CPU_CLK_THREAD_UNHALTED.REF_XCLK

# Reference cycles when the thread is unhalted (counts at 100 MHz rate).
3C.01 CPU_CLK_UNHALTED.REF_XCLK

# Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
3C.01.AnyT CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY

# Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
3C.01.AnyT CPU_CLK_UNHALTED.REF_XCLK_ANY

# Count XClk pulses when this thread is unhalted and the other is halted.
3C.02 CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE

# Count XClk pulses when this thread is unhalted and the other thread is halted.
3C.02 CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE

# Cycles with L1D load Misses outstanding from any thread on physical core.
48.01.CMSK=1.AnyT.CTR=2 L1D_PEND_MISS.PENDING_CYCLES_ANY

# Cycles with L1D load Misses outstanding.
48.01.CMSK=1.CTR=2 L1D_PEND_MISS.PENDING_CYCLES

# L1D miss oustandings duration in cycles.
48.01.CTR=2 L1D_PEND_MISS.PENDING

# Cycles a demand request was blocked due to Fill Buffers inavailability.
48.02.CMSK=1 L1D_PEND_MISS.FB_FULL

# Store misses in all DTLB levels that cause page walks.
49.01 DTLB_STORE_MISSES.MISS_CAUSES_A_WALK

# Store misses in all DTLB levels that cause completed page walks.
49.02 DTLB_STORE_MISSES.WALK_COMPLETED

# Cycles when PMH is busy with page walks.
49.04 DTLB_STORE_MISSES.WALK_DURATION

# Store operations that miss the first TLB level but hit the second and do not cause page walks.
49.10 DTLB_STORE_MISSES.STLB_HIT

# Not software-prefetch load dispatches that hit FB allocated for software prefetch.
4C.01 LOAD_HIT_PRE.SW_PF

# Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.
4C.02 LOAD_HIT_PRE.HW_PF

# Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .
4E.02 HW_PRE_REQ.DL1_MISS

# Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
4F.10 EPT.WALK_CYCLES

# L1D data line replacements.
51.01 L1D.REPLACEMENT

# Allocated L1D data cache lines in M state.
51.02 L1D.ALLOCATED_IN_M

# L1D data cache lines in M state evicted due to replacement.
51.04 L1D.EVICTION

# Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.
51.08 L1D.ALL_M_REPLACEMENT

# Increments the number of flags-merge uops in flight each cycle.
59.20 PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP

# Performance sensitive flags-merging uops added by Sandy Bridge u-arch.
59.20.CMSK=1 PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES

# Cycles with at least one slow LEA uop being allocated.
59.40 PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW

# Multiply packed/scalar single precision uops allocated.
59.80 PARTIAL_RAT_STALLS.MUL_SINGLE_UOP

# Cycles with either free list is empty.
5B.0C RESOURCE_STALLS2.ALL_FL_EMPTY

# Resource stalls2 control structures full for physical registers.
5B.0F RESOURCE_STALLS2.ALL_PRF_CONTROL

# Cycles when Allocator is stalled if BOB is full and new branch needs it.
5B.40 RESOURCE_STALLS2.BOB_FULL

# Resource stalls out of order resources full.
5B.4F RESOURCE_STALLS2.OOO_RSRC

# Unhalted core cycles when the thread is in ring 0.
5C.01 CPL_CYCLES.RING0

# Number of intervals between processor halts while thread is in ring 0.
5C.01.CMSK=1.EDG CPL_CYCLES.RING0_TRANS

# Unhalted core cycles when thread is in rings 1, 2, or 3.
5C.02 CPL_CYCLES.RING123

# Cycles when Reservation Station (RS) is empty for the thread.
5E.01 RS_EVENTS.EMPTY_CYCLES

# Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
5E.01.CMSK=1.EDG.INV RS_EVENTS.EMPTY_END

# Offcore outstanding Demand Data Read transactions in uncore queue.
60.01 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD

# Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.
60.01.CMSK=1 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD

# Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.
60.01.CMSK=6 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6

# Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.
60.04 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO

# Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.
60.04.CMSK=1 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO

# Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.
60.08 OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD

# Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.
60.08.CMSK=1 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD

# Cycles when L1 and L2 are locked due to UC or split lock.
63.01 LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION

# Cycles when L1D is locked.
63.02 LOCK_CYCLES.CACHE_LOCK_DURATION

# Instruction Decode Queue (IDQ) empty cycles.
79.02 IDQ.EMPTY

# Uops delivered to Instruction Decode Queue (IDQ) from MITE path.
79.04 IDQ.MITE_UOPS

# Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.
79.04.CMSK=1 IDQ.MITE_CYCLES

# Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.
79.08 IDQ.DSB_UOPS

# Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.
79.08.CMSK=1 IDQ.DSB_CYCLES

# Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
79.10 IDQ.MS_DSB_UOPS

# Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
79.10.CMSK=1 IDQ.MS_DSB_CYCLES

# Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.
79.10.CMSK=1.EDG IDQ.MS_DSB_OCCUR

# Cycles Decode Stream Buffer (DSB) is delivering any Uop.
79.18.CMSK=1 IDQ.ALL_DSB_CYCLES_ANY_UOPS

# Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.
79.18.CMSK=4 IDQ.ALL_DSB_CYCLES_4_UOPS

# Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
79.20 IDQ.MS_MITE_UOPS

# Cycles MITE is delivering any Uop.
79.24.CMSK=1 IDQ.ALL_MITE_CYCLES_ANY_UOPS

# Cycles MITE is delivering 4 Uops.
79.24.CMSK=4 IDQ.ALL_MITE_CYCLES_4_UOPS

# Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
79.30 IDQ.MS_UOPS

# Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
79.30.CMSK=1 IDQ.MS_CYCLES

# Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.
79.30.CMSK=1.EDG IDQ.MS_SWITCHES

# Uops delivered to Instruction Decode Queue (IDQ) from MITE path.
79.3C IDQ.MITE_ALL_UOPS

# Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.
80.01 ICACHE.HIT

# Instruction cache, streaming buffer and victim cache misses.
80.02 ICACHE.MISSES

# Misses at all ITLB levels that cause page walks.
85.01 ITLB_MISSES.MISS_CAUSES_A_WALK

# Misses in all ITLB levels that cause completed page walks.
85.02 ITLB_MISSES.WALK_COMPLETED

# Cycles when PMH is busy with page walks.
85.04 ITLB_MISSES.WALK_DURATION

# Operations that miss the first ITLB level but hit the second and do not cause any page walks.
85.10 ITLB_MISSES.STLB_HIT

# Stalls caused by changing prefix length of the instruction.
87.01 ILD_STALL.LCP

# Stall cycles because IQ is full.
87.04 ILD_STALL.IQ_FULL

# Not taken macro-conditional branches.
88.41 BR_INST_EXEC.NONTAKEN_CONDITIONAL

# Taken speculative and retired macro-conditional branches.
88.81 BR_INST_EXEC.TAKEN_CONDITIONAL

# Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.
88.82 BR_INST_EXEC.TAKEN_DIRECT_JUMP

# Taken speculative and retired indirect branches excluding calls and returns.
88.84 BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET

# Taken speculative and retired indirect branches with return mnemonic.
88.88 BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN

# Taken speculative and retired direct near calls.
88.90 BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL

# Taken speculative and retired indirect calls.
88.A0 BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL

# Speculative and retired macro-conditional branches.
88.C1 BR_INST_EXEC.ALL_CONDITIONAL

# Speculative and retired macro-unconditional branches excluding calls and indirects.
88.C2 BR_INST_EXEC.ALL_DIRECT_JMP

# Speculative and retired indirect branches excluding calls and returns.
88.C4 BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET

# Speculative and retired indirect return branches.
88.C8 BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN

# Speculative and retired direct near calls.
88.D0 BR_INST_EXEC.ALL_DIRECT_NEAR_CALL

# Speculative and retired  branches.
88.FF BR_INST_EXEC.ALL_BRANCHES

# Not taken speculative and retired mispredicted macro conditional branches.
89.41 BR_MISP_EXEC.NONTAKEN_CONDITIONAL

# Taken speculative and retired mispredicted macro conditional branches.
89.81 BR_MISP_EXEC.TAKEN_CONDITIONAL

# Taken speculative and retired mispredicted indirect branches excluding calls and returns.
89.84 BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET

# Taken speculative and retired mispredicted indirect branches with return mnemonic.
89.88 BR_MISP_EXEC.TAKEN_RETURN_NEAR

# Taken speculative and retired mispredicted direct near calls.
89.90 BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL

# Taken speculative and retired mispredicted indirect calls.
89.A0 BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL

# Speculative and retired mispredicted macro conditional branches.
89.C1 BR_MISP_EXEC.ALL_CONDITIONAL

# Mispredicted indirect branches excluding calls and returns.
89.C4 BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET

# Speculative and retired mispredicted direct near calls.
89.D0 BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL

# Speculative and retired mispredicted macro conditional branches.
89.FF BR_MISP_EXEC.ALL_BRANCHES

# Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .
9C.01 IDQ_UOPS_NOT_DELIVERED.CORE

# Cycles with less than 3 uops delivered by the front end.
9C.01.CMSK=1 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE

# Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
9C.01.CMSK=1.INV IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK

# Cycles with less than 2 uops delivered by the front end.
9C.01.CMSK=2 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE

# Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
9C.01.CMSK=3 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE

# Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
9C.01.CMSK=4 IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE

# Cycles when 1 or more uops were delivered to the by the front end.
9C.01.CMSK=4.INV IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE

# Cycles per thread when uops are dispatched to port 0.
A1.01 UOPS_DISPATCHED_PORT.PORT_0

# Cycles per core when uops are dispatched to port 0.
A1.01.AnyT UOPS_DISPATCHED_PORT.PORT_0_CORE

# Cycles per thread when uops are dispatched to port 1.
A1.02 UOPS_DISPATCHED_PORT.PORT_1

# Cycles per core when uops are dispatched to port 1.
A1.02.AnyT UOPS_DISPATCHED_PORT.PORT_1_CORE

# Cycles per thread when load or STA uops are dispatched to port 2.
A1.0C UOPS_DISPATCHED_PORT.PORT_2

# Cycles per core when load or STA uops are dispatched to port 2.
A1.0C.AnyT UOPS_DISPATCHED_PORT.PORT_2_CORE

# Cycles per thread when load or STA uops are dispatched to port 3.
A1.30 UOPS_DISPATCHED_PORT.PORT_3

# Cycles per core when load or STA uops are dispatched to port 3.
A1.30.AnyT UOPS_DISPATCHED_PORT.PORT_3_CORE

# Cycles per thread when uops are dispatched to port 4.
A1.40 UOPS_DISPATCHED_PORT.PORT_4

# Cycles per core when uops are dispatched to port 4.
A1.40.AnyT UOPS_DISPATCHED_PORT.PORT_4_CORE

# Cycles per thread when uops are dispatched to port 5.
A1.80 UOPS_DISPATCHED_PORT.PORT_5

# Cycles per core when uops are dispatched to port 5.
A1.80.AnyT UOPS_DISPATCHED_PORT.PORT_5_CORE

# Resource-related stall cycles.
A2.01 RESOURCE_STALLS.ANY

# Counts the cycles of stall due to lack of load buffers.
A2.02 RESOURCE_STALLS.LB

# Cycles stalled due to no eligible RS entry available.
A2.04 RESOURCE_STALLS.RS

# Cycles stalled due to no store buffers available. (not including draining form sync).
A2.08 RESOURCE_STALLS.SB

# Resource stalls due to load or store buffers all being in use.
A2.0A RESOURCE_STALLS.LB_SB

# Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.
A2.0E RESOURCE_STALLS.MEM_RS

# Cycles stalled due to re-order buffer full.
A2.10 RESOURCE_STALLS.ROB

# Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.
A2.F0 RESOURCE_STALLS.OOO_RSRC

# Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.
A3.01.CMSK=1 CYCLE_ACTIVITY.CYCLES_L2_PENDING

# Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.
A3.02.CMSK=2.CTR=2 CYCLE_ACTIVITY.CYCLES_L1D_PENDING

# Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.
A3.04.CMSK=4 CYCLE_ACTIVITY.CYCLES_NO_DISPATCH

# Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.
A3.05.CMSK=5 CYCLE_ACTIVITY.STALLS_L2_PENDING

# Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.
A3.06.CMSK=6.CTR=2 CYCLE_ACTIVITY.STALLS_L1D_PENDING

# Number of Uops delivered by the LSD.
A8.01 LSD.UOPS

# Cycles Uops delivered by the LSD, but didn't come from the decoder.
A8.01.CMSK=1 LSD.CYCLES_ACTIVE

# Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.
A8.01.CMSK=4 LSD.CYCLES_4_UOPS

# Decode Stream Buffer (DSB)-to-MITE switches.
AB.01 DSB2MITE_SWITCHES.COUNT

# Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.
AB.02 DSB2MITE_SWITCHES.PENALTY_CYCLES

# Cases of cancelling valid DSB fill not because of exceeding way limit.
AC.02 DSB_FILL.OTHER_CANCEL

# Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.
AC.08 DSB_FILL.EXCEED_DSB_LINES

# Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.
AC.0A DSB_FILL.ALL_CANCEL

# Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.
AE.01 ITLB.ITLB_FLUSH

# Demand Data Read requests sent to uncore.
B0.01 OFFCORE_REQUESTS.DEMAND_DATA_RD

# Cacheable and noncachaeble code read requests.
B0.02 OFFCORE_REQUESTS.DEMAND_CODE_RD

# Demand RFO requests including regular RFOs, locks, ItoM.
B0.04 OFFCORE_REQUESTS.DEMAND_RFO

# Demand and prefetch data reads.
B0.08 OFFCORE_REQUESTS.ALL_DATA_RD

# Uops dispatched per thread.
B1.01 UOPS_DISPATCHED.THREAD

# Uops dispatched from any thread.
B1.02 UOPS_DISPATCHED.CORE

# Cycles at least 1 micro-op is executed from any thread on physical core.
B1.02.CMSK=1 UOPS_EXECUTED.CORE_CYCLES_GE_1

# Cycles at least 2 micro-op is executed from any thread on physical core.
B1.02.CMSK=2 UOPS_EXECUTED.CORE_CYCLES_GE_2

# Cycles at least 3 micro-op is executed from any thread on physical core.
B1.02.CMSK=3 UOPS_EXECUTED.CORE_CYCLES_GE_3

# Cycles at least 4 micro-op is executed from any thread on physical core.
B1.02.CMSK=4 UOPS_EXECUTED.CORE_CYCLES_GE_4

# Cycles with no micro-ops executed from any thread on physical core.
B1.02.INV UOPS_EXECUTED.CORE_CYCLES_NONE

# Cases when offcore requests buffer cannot take more entries for core.
B2.01 OFFCORE_REQUESTS_BUFFER.SQ_FULL

# This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.
B6.01 AGU_BYPASS_CANCEL.COUNT

# DTLB flush attempts of the thread-specific entries.
BD.01 TLB_FLUSH.DTLB_THREAD

# STLB flush attempts.
BD.20 TLB_FLUSH.STLB_ANY

# Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.
BE.01 PAGE_WALKS.LLC_MISS

# Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.
BF.05.CMSK=1 L1D_BLOCKS.BANK_CONFLICT_CYCLES

# Number of instructions retired. General Counter   - architectural event.
C0.00 INST_RETIRED.ANY_P

# Instructions retired. (Precise Event - PEBS).
C0.01.CTR=1.TakenAlone INST_RETIRED.PREC_DIST

# Retired instructions experiencing ITLB misses.
C1.02 OTHER_ASSISTS.ITLB_MISS_RETIRED

# Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.
C1.08 OTHER_ASSISTS.AVX_STORE

# Number of transitions from AVX-256 to legacy SSE when penalty applicable.
C1.10 OTHER_ASSISTS.AVX_TO_SSE

# Number of transitions from SSE to AVX-256 when penalty applicable.
C1.20 OTHER_ASSISTS.SSE_TO_AVX

# Actually retired uops. (Precise Event - PEBS).
C2.01 UOPS_RETIRED.ALL

# Cycles without actually retired uops.
C2.01.CMSK=1.INV UOPS_RETIRED.CORE_STALL_CYCLES

# Cycles without actually retired uops.
C2.01.CMSK=1.INV UOPS_RETIRED.STALL_CYCLES

# Cycles with less than 10 actually retired uops.
C2.01.CMSK=10.INV UOPS_RETIRED.TOTAL_CYCLES

# Retirement slots used. (Precise Event - PEBS).
C2.02 UOPS_RETIRED.RETIRE_SLOTS

# Number of machine clears (nukes) of any type.
C3.01.CMSK=1.EDG MACHINE_CLEARS.COUNT

# Counts the number of machine clears due to memory order conflicts.
C3.02 MACHINE_CLEARS.MEMORY_ORDERING

# Self-modifying code (SMC) detected.
C3.04 MACHINE_CLEARS.SMC

# This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
C3.20 MACHINE_CLEARS.MASKMOV

# All (macro) branch instructions retired.
C4.00 BR_INST_RETIRED.ALL_BRANCHES

# Conditional branch instructions retired. (Precise Event - PEBS).
C4.01 BR_INST_RETIRED.CONDITIONAL

# Direct and indirect near call instructions retired. (Precise Event - PEBS).
C4.02 BR_INST_RETIRED.NEAR_CALL

# Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).
C4.02 BR_INST_RETIRED.NEAR_CALL_R3

# All (macro) branch instructions retired. (Precise Event - PEBS).
C4.04 BR_INST_RETIRED.ALL_BRANCHES_PEBS

# Return instructions retired. (Precise Event - PEBS).
C4.08 BR_INST_RETIRED.NEAR_RETURN

# Not taken branch instructions retired.
C4.10 BR_INST_RETIRED.NOT_TAKEN

# Taken branch instructions retired. (Precise Event - PEBS).
C4.20 BR_INST_RETIRED.NEAR_TAKEN

# Far branch instructions retired.
C4.40 BR_INST_RETIRED.FAR_BRANCH

# All mispredicted macro branch instructions retired.
C5.00 BR_MISP_RETIRED.ALL_BRANCHES

# Mispredicted conditional branch instructions retired. (Precise Event - PEBS).
C5.01 BR_MISP_RETIRED.CONDITIONAL

# Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).
C5.02 BR_MISP_RETIRED.NEAR_CALL

# Mispredicted macro branch instructions retired. (Precise Event - PEBS).
C5.04 BR_MISP_RETIRED.ALL_BRANCHES_PEBS

# Mispredicted not taken branch instructions retired.(Precise Event - PEBS).
C5.10 BR_MISP_RETIRED.NOT_TAKEN

# Mispredicted taken branch instructions retired. (Precise Event - PEBS).
C5.20 BR_MISP_RETIRED.TAKEN

# Number of X87 assists due to output value.
CA.02 FP_ASSIST.X87_OUTPUT

# Number of X87 assists due to input value.
CA.04 FP_ASSIST.X87_INPUT

# Number of SIMD FP assists due to Output values.
CA.08 FP_ASSIST.SIMD_OUTPUT

# Number of SIMD FP assists due to input values.
CA.10 FP_ASSIST.SIMD_INPUT

# Cycles with any input/output SSE or FP assist.
CA.1E.CMSK=1 FP_ASSIST.ANY

# Count cases of saving new LBR.
CC.20 ROB_MISC_EVENTS.LBR_INSERTS

# Loads with latency value being above 16.
CD.01.MSR_3F6H=0x10.CTR=3.TakenAlone MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16

# Loads with latency value being above 256.
CD.01.MSR_3F6H=0x100.CTR=3.TakenAlone MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256

# Loads with latency value being above 32.
CD.01.MSR_3F6H=0x20.CTR=3.TakenAlone MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32

# Loads with latency value being above 512.
CD.01.MSR_3F6H=0x200.CTR=3.TakenAlone MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512

# Loads with latency value being above 4 .
CD.01.MSR_3F6H=0x4.CTR=3.TakenAlone MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4

# Loads with latency value being above 64.
CD.01.MSR_3F6H=0x40.CTR=3.TakenAlone MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64

# Loads with latency value being above 8.
CD.01.MSR_3F6H=0x8.CTR=3.TakenAlone MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8

# Loads with latency value being above 128.
CD.01.MSR_3F6H=0x80.CTR=3.TakenAlone MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128

# Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).
CD.02.CTR=3.TakenAlone MEM_TRANS_RETIRED.PRECISE_STORE

# Retired load uops that miss the STLB. (Precise Event - PEBS).
D0.11 MEM_UOPS_RETIRED.STLB_MISS_LOADS

# Retired store uops that miss the STLB. (Precise Event - PEBS).
D0.12 MEM_UOPS_RETIRED.STLB_MISS_STORES

# Retired load uops with locked access. (Precise Event - PEBS).
D0.21 MEM_UOPS_RETIRED.LOCK_LOADS

# Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).
D0.41 MEM_UOPS_RETIRED.SPLIT_LOADS

# Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).
D0.42 MEM_UOPS_RETIRED.SPLIT_STORES

# All retired load uops. (Precise Event - PEBS).
D0.81 MEM_UOPS_RETIRED.ALL_LOADS

# All retired store uops. (Precise Event - PEBS).
D0.82 MEM_UOPS_RETIRED.ALL_STORES

# Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).
D1.01 MEM_LOAD_UOPS_RETIRED.L1_HIT

# Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).
D1.02 MEM_LOAD_UOPS_RETIRED.L2_HIT

# Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).
D1.04 MEM_LOAD_UOPS_RETIRED.LLC_HIT

# Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).
D1.40 MEM_LOAD_UOPS_RETIRED.HIT_LFB

# Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).
D2.01 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS

# Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).
D2.02 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT

# Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).
D2.04 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM

# Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).
D2.08 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE

# Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).
D4.02 MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS

# Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
E6.1F BACLEARS.ANY

# Demand Data Read requests that access L2 cache.
F0.01 L2_TRANS.DEMAND_DATA_RD

# RFO requests that access L2 cache.
F0.02 L2_TRANS.RFO

# L2 cache accesses when fetching instructions.
F0.04 L2_TRANS.CODE_RD

# L2 or LLC HW prefetches that access L2 cache.
F0.08 L2_TRANS.ALL_PF

# L1D writebacks that access L2 cache.
F0.10 L2_TRANS.L1D_WB

# L2 fill requests that access L2 cache.
F0.20 L2_TRANS.L2_FILL

# L2 writebacks that access L2 cache.
F0.40 L2_TRANS.L2_WB

# Transactions accessing L2 pipe.
F0.80 L2_TRANS.ALL_REQUESTS

# L2 cache lines in I state filling L2.
F1.01 L2_LINES_IN.I

# L2 cache lines in S state filling L2.
F1.02 L2_LINES_IN.S

# L2 cache lines in E state filling L2.
F1.04 L2_LINES_IN.E

# L2 cache lines filling L2.
F1.07 L2_LINES_IN.ALL

# Clean L2 cache lines evicted by demand.
F2.01 L2_LINES_OUT.DEMAND_CLEAN

# Dirty L2 cache lines evicted by demand.
F2.02 L2_LINES_OUT.DEMAND_DIRTY

# Clean L2 cache lines evicted by L2 prefetch.
F2.04 L2_LINES_OUT.PF_CLEAN

# Dirty L2 cache lines evicted by L2 prefetch.
F2.08 L2_LINES_OUT.PF_DIRTY

# Dirty L2 cache lines filling the L2.
F2.0A L2_LINES_OUT.DIRTY_ALL

# Split locks in SQ.
F4.10 SQ_MISC.SPLIT_LOCK