nanoBench/configs/cfg_Nehalem_all.txt

# Performance monitoring events for processors based on the Nehalem microarchitecture.
# Applies to processors with DisplayFamily_DisplayModel of 06_1AH, 06_1EH, 06_1FH, and 06_2EH.
# See Table 19-20 of Intel's "System Programming Guide" (Jan. 2019)

04.07 SB_DRAIN.ANY
06.04 STORE_BLOCKS.AT_RET
06.08 STORE_BLOCKS.L1D_BLOCK
07.01 PARTIAL_ADDRESS_ALIAS
08.01 DTLB_LOAD_MISSES.ANY
08.02 DTLB_LOAD_MISSES.WALK_COMPLETED
08.10 DTLB_LOAD_MISSES.STLB_HIT
08.20 DTLB_LOAD_MISSES.PDE_MISS
08.80 DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED
0B.01 MEM_INST_RETIRED.LOADS
0B.02 MEM_INST_RETIRED.STORES
0B.10 MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD
0C.01 MEM_STORE_RETIRED.DTLB_MISS
0E.01 UOPS_ISSUED.ANY
0E.01.CMSK=1.INV UOPS_ISSUED.STALLED_CYCLES
0E.02 UOPS_ISSUED.FUSED
0F.02 MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM
0F.08 MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT
0F.10 MEM_UNCORE_RETIRED.REMOTE_DRAM
0F.20 MEM_UNCORE_RETIRED.LOCAL_DRAM
10.01 FP_COMP_OPS_EXE.X87
10.02 FP_COMP_OPS_EXE.MMX
10.04 FP_COMP_OPS_EXE.SSE_FP
10.08 FP_COMP_OPS_EXE.SSE2_INTEGER
10.10 FP_COMP_OPS_EXE.SSE_FP_PACKED
10.20 FP_COMP_OPS_EXE.SSE_FP_SCALAR
10.40 FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION
10.80 FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION
12.01 SIMD_INT_128.PACKED_MPY
12.02 SIMD_INT_128.PACKED_SHIFT
12.04 SIMD_INT_128.PACK
12.08 SIMD_INT_128.UNPACK
12.10 SIMD_INT_128.PACKED_LOGICAL
12.20 SIMD_INT_128.PACKED_ARITH
12.40 SIMD_INT_128.SHUFFLE_MOVE
13.01 LOAD_DISPATCH.RS
13.02 LOAD_DISPATCH.RS_DELAYED
13.04 LOAD_DISPATCH.MOB
13.07 LOAD_DISPATCH.ANY
14.01 ARITH.CYCLES_DIV_BUSY
14.02 ARITH.MUL
17.01 INST_QUEUE_WRITES
18.01 INST_DECODED.DEC0
19.01 TWO_UOP_INSTS_DECODED
1E.01 INST_QUEUE_WRITE_CYCLES
20.01 LSD_OVERFLOW
24.01 L2_RQSTS.LD_HIT
24.02 L2_RQSTS.LD_MISS
24.03 L2_RQSTS.LOADS
24.04 L2_RQSTS.RFO_HIT
24.08 L2_RQSTS.RFO_MISS
24.0C L2_RQSTS.RFOS
24.10 L2_RQSTS.IFETCH_HIT
24.20 L2_RQSTS.IFETCH_MISS
24.30 L2_RQSTS.IFETCHES
24.40 L2_RQSTS.PREFETCH_HIT
24.80 L2_RQSTS.PREFETCH_MISS
24.C0 L2_RQSTS.PREFETCHES
24.AA L2_RQSTS.MISS
24.FF L2_RQSTS.REFERENCES
26.01 L2_DATA_RQSTS.DEMAND.I_STATE
26.02 L2_DATA_RQSTS.DEMAND.S_STATE
26.04 L2_DATA_RQSTS.DEMAND.E_STATE
26.08 L2_DATA_RQSTS.DEMAND.M_STATE
26.0F L2_DATA_RQSTS.DEMAND.MESI
26.10 L2_DATA_RQSTS.PREFETCH.I_STATE
26.20 L2_DATA_RQSTS.PREFETCH.S_STATE
26.40 L2_DATA_RQSTS.PREFETCH.E_STATE
26.80 L2_DATA_RQSTS.PREFETCH.M_STATE
26.F0 L2_DATA_RQSTS.PREFETCH.MESI
26.FF L2_DATA_RQSTS.ANY
27.01 L2_WRITE.RFO.I_STATE
27.02 L2_WRITE.RFO.S_STATE
27.08 L2_WRITE.RFO.M_STATE
27.0E L2_WRITE.RFO.HIT
27.0F L2_WRITE.RFO.MESI
27.10 L2_WRITE.LOCK.I_STATE
27.20 L2_WRITE.LOCK.S_STATE
27.40 L2_WRITE.LOCK.E_STATE
27.80 L2_WRITE.LOCK.M_STATE
27.E0 L2_WRITE.LOCK.HIT
27.F0 L2_WRITE.LOCK.MESI
28.01 L1D_WB_L2.I_STATE
28.02 L1D_WB_L2.S_STATE
28.04 L1D_WB_L2.E_STATE
28.08 L1D_WB_L2.M_STATE
28.0F L1D_WB_L2.MESI
2E.4F L3_LAT_CACHE.REFERENCE
2E.41 L3_LAT_CACHE.MISS
3C.00 CPU_CLK_UNHALTED.THREAD_P
3C.01 CPU_CLK_UNHALTED.REF_P
40.01.CTR=0 L1D_CACHE_LD.I_STATE
40.02.CTR=0 L1D_CACHE_LD.S_STATE
40.04.CTR=0 L1D_CACHE_LD.E_STATE
40.08.CTR=0 L1D_CACHE_LD.M_STATE
40.0F.CTR=0 L1D_CACHE_LD.MESI
41.02.CTR=0 L1D_CACHE_ST.S_STATE
41.04.CTR=0 L1D_CACHE_ST.E_STATE
41.08.CTR=0 L1D_CACHE_ST.M_STATE
42.01.CTR=0 L1D_CACHE_LOCK.HIT
42.02.CTR=0 L1D_CACHE_LOCK.S_STATE
42.04.CTR=0 L1D_CACHE_LOCK.E_STATE
42.08.CTR=0 L1D_CACHE_LOCK.M_STATE
43.01.CTR=0 L1D_ALL_REF.ANY
43.02.CTR=0 L1D_ALL_REF.CACHEABLE
49.01 DTLB_MISSES.ANY
49.02 DTLB_MISSES.WALK_COMPLETED
49.10 DTLB_MISSES.STLB_HIT
49.20 DTLB_MISSES.PDE_MISS
49.80 DTLB_MISSES.LARGE_WALK_COMPLETED
4C.01 LOAD_HIT_PRE
4E.01 L1D_PREFETCH.REQUESTS
4E.02 L1D_PREFETCH.MISS
4E.04 L1D_PREFETCH.TRIGGERS
51.01.CTR=0 L1D.REPL
51.02.CTR=0 L1D.M_REPL
51.04.CTR=0 L1D.M_EVICT
51.08.CTR=0 L1D.M_SNOOP_EVICT
52.01 L1D_CACHE_PREFETCH_LOCK_FB_HIT
53.01 L1D_CACHE_LOCK_FB_HIT
63.01.CTR=0 CACHE_LOCK_CYCLES.L1D_L2
63.02.CTR=0 CACHE_LOCK_CYCLES.L1D
6C.01 IO_TRANSACTIONS
80.01 L1I.HITS
80.02 L1I.MISSES
80.03 L1I.READS
80.04 L1I.CYCLES_STALLED
82.01 LARGE_ITLB.HIT
85.01 ITLB_MISSES.ANY
85.02 ITLB_MISSES.WALK_COMPLETED
87.01 ILD_STALL.LCP
87.02 ILD_STALL.MRU
87.04 ILD_STALL.IQ_FULL
87.08 ILD_STALL.REGEN
87.0F ILD_STALL.ANY
88.01 BR_INST_EXEC.COND
88.02 BR_INST_EXEC.DIRECT
88.04 BR_INST_EXEC.INDIRECT_NON_CALL
88.07 BR_INST_EXEC.NON_CALLS
88.08 BR_INST_EXEC.RETURN_NEAR
88.10 BR_INST_EXEC.DIRECT_NEAR_CALL
88.20 BR_INST_EXEC.INDIRECT_NEAR_CALL
88.30 BR_INST_EXEC.NEAR_CALLS
88.40 BR_INST_EXEC.TAKEN
88.7F BR_INST_EXEC.ANY
89.01 BR_MISP_EXEC.COND
89.02 BR_MISP_EXEC.DIRECT
89.04 BR_MISP_EXEC.INDIRECT_NON_CALL
89.07 BR_MISP_EXEC.NON_CALLS
89.08 BR_MISP_EXEC.RETURN_NEAR
89.10 BR_MISP_EXEC.DIRECT_NEAR_CALL
89.20 BR_MISP_EXEC.INDIRECT_NEAR_CALL
89.30 BR_MISP_EXEC.NEAR_CALLS
89.40 BR_MISP_EXEC.TAKEN
89.7F BR_MISP_EXEC.ANY
A2.01 RESOURCE_STALLS.ANY
A2.02 RESOURCE_STALLS.LOAD
A2.04 RESOURCE_STALLS.RS_FULL
A2.08 RESOURCE_STALLS.STORE
A2.10 RESOURCE_STALLS.ROB_FULL
A2.20 RESOURCE_STALLS.FPCW
A2.40 RESOURCE_STALLS.MXCSR
A2.80 RESOURCE_STALLS.OTHER
A6.01 MACRO_INSTS.FUSIONS_DECODED
A7.01 BACLEAR_FORCE_IQ
A8.01 LSD.UOPS
AE.01 ITLB_FLUSH
B0.40 OFFCORE_REQUESTS.L1D_WRITEBACK
B1.01 UOPS_EXECUTED.PORT0
B1.02 UOPS_EXECUTED.PORT1
B1.04 UOPS_EXECUTED.PORT2_CORE
B1.08 UOPS_EXECUTED.PORT3_CORE
B1.10 UOPS_EXECUTED.PORT4_CORE
B1.1F UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5
B1.20 UOPS_EXECUTED.PORT5
B1.3F UOPS_EXECUTED.CORE_ACTIVE_CYCLES
B1.40 UOPS_EXECUTED.PORT015
B1.80 UOPS_EXECUTED.PORT234
B2.01 OFFCORE_REQUESTS_SQ_FULL
B8.01 SNOOP_RESPONSE.HIT
B8.02 SNOOP_RESPONSE.HITE
B8.04 SNOOP_RESPONSE.HITM
C0.00 INST_RETIRED.ANY_P
C0.02 INST_RETIRED.X87
C0.04 INST_RETIRED.MMX
C2.01 UOPS_RETIRED.ANY
C2.02 UOPS_RETIRED.RETIRE_SLOTS
C2.04 UOPS_RETIRED.MACRO_FUSED
C3.01 MACHINE_CLEARS.CYCLES
C3.02 MACHINE_CLEARS.MEM_ORDER
C3.04 MACHINE_CLEARS.SMC
C4.00 BR_INST_RETIRED.ALL_BRANCHES
C4.01 BR_INST_RETIRED.CONDITIONAL
C4.02 BR_INST_RETIRED.NEAR_CALL
C5.00 BR_MISP_RETIRED.ALL_BRANCHES
C5.02 BR_MISP_RETIRED.NEAR_CALL
C7.01 SSEX_UOPS_RETIRED.PACKED_SINGLE
C7.02 SSEX_UOPS_RETIRED.SCALAR_SINGLE
C7.04 SSEX_UOPS_RETIRED.PACKED_DOUBLE
C7.08 SSEX_UOPS_RETIRED.SCALAR_DOUBLE
C7.10 SSEX_UOPS_RETIRED.VECTOR_INTEGER
C8.20 ITLB_MISS_RETIRED
CB.01 MEM_LOAD_RETIRED.L1D_HIT
CB.02 MEM_LOAD_RETIRED.L2_HIT
CB.04 MEM_LOAD_RETIRED.L3_UNSHARED_HIT
CB.08 MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM
CB.10 MEM_LOAD_RETIRED.L3_MISS
CB.40 MEM_LOAD_RETIRED.HIT_LFB
CB.80 MEM_LOAD_RETIRED.DTLB_MISS
CC.01 FP_MMX_TRANS.TO_FP
CC.02 FP_MMX_TRANS.TO_MMX
CC.03 FP_MMX_TRANS.ANY
D0.01 MACRO_INSTS.DECODED
D1.02 UOPS_DECODED.MS
D1.04 UOPS_DECODED.ESP_FOLDING
D1.08 UOPS_DECODED.ESP_SYNC
D2.01 RAT_STALLS.FLAGS
D2.02 RAT_STALLS.REGISTERS
D2.04 RAT_STALLS.ROB_READ_PORT
D2.08 RAT_STALLS.SCOREBOARD
D2.0F RAT_STALLS.ANY
D4.01 SEG_RENAME_STALLS
D5.01 ES_REG_RENAMES
DB.01 UOP_UNFUSION
E0.01 BR_INST_DECODED
E5.01 BPU_MISSED_CALL_RET
E6.01 BACLEAR.CLEAR
E6.02 BACLEAR.BAD_TARGET
E8.01 BPU_CLEARS.EARLY
E8.02 BPU_CLEARS.LATE
F0.01 L2_TRANSACTIONS.LOAD
F0.02 L2_TRANSACTIONS.RFO
F0.04 L2_TRANSACTIONS.IFETCH
F0.08 L2_TRANSACTIONS.PREFETCH
F0.10 L2_TRANSACTIONS.L1D_WB
F0.20 L2_TRANSACTIONS.FILL
F0.40 L2_TRANSACTIONS.WB
F0.80 L2_TRANSACTIONS.ANY
F1.02 L2_LINES_IN.S_STATE
F1.04 L2_LINES_IN.E_STATE
F1.07 L2_LINES_IN.ANY
F2.01 L2_LINES_OUT.DEMAND_CLEAN
F2.02 L2_LINES_OUT.DEMAND_DIRTY
F2.04 L2_LINES_OUT.PREFETCH_CLEAN
F2.08 L2_LINES_OUT.PREFETCH_DIRTY
F2.0F L2_LINES_OUT.ANY
F4.10 SQ_MISC.SPLIT_LOCK
F6.01 SQ_FULL_STALL_CYCLES
F7.01 FP_ASSIST.ALL
F7.02 FP_ASSIST.OUTPUT
F7.04 FP_ASSIST.INPUT
FD.01 SIMD_INT_64.PACKED_MPY
FD.02 SIMD_INT_64.PACKED_SHIFT
FD.04 SIMD_INT_64.PACK
FD.08 SIMD_INT_64.UNPACK
FD.10 SIMD_INT_64.PACKED_LOGICAL
FD.20 SIMD_INT_64.PACKED_ARITH
FD.40 SIMD_INT_64.SHUFFLE_MOVE