mirror of
https://github.com/andreas-abel/nanoBench.git
synced 2025-07-21 15:11:03 +02:00
243 lines
8.5 KiB
Plaintext
243 lines
8.5 KiB
Plaintext
# Performance monitoring events for processors based on the Sandy Bridge microarchitecture.
|
|
# Applies to processors with DisplayFamily_DisplayModel of 06_2AH and 06_2DH.
|
|
# See Table 19-16 of Intel's "System Programming Guide" (Jan. 2019)
|
|
|
|
03.01 LD_BLOCKS.DATA_UNKNOWN
|
|
03.02 LD_BLOCKS.STORE_FORWARD
|
|
03.08 LD_BLOCKS.NO_SR
|
|
03.10 LD_BLOCKS.ALL_BLOCK
|
|
05.01 MISALIGN_MEM_REF.LOADS
|
|
05.02 MISALIGN_MEM_REF.STORES
|
|
07.01 LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
|
|
07.08 LD_BLOCKS_PARTIAL.ALL_STA_BLOCK
|
|
08.01 DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
|
|
08.02 DTLB_LOAD_MISSES.WALK_COMPLETED
|
|
08.04 DTLB_LOAD_MISSES.WALK_DURATION
|
|
08.10 DTLB_LOAD_MISSES.STLB_HIT
|
|
0D.03.CMSK=1 INT_MISC.RECOVERY_CYCLES
|
|
0D.40 INT_MISC.RAT_STALL_CYCLES
|
|
0E.01 UOPS_ISSUED.ANY
|
|
10.01 FP_COMP_OPS_EXE.X87
|
|
10.10 FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE
|
|
10.20 FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE
|
|
10.40 FP_COMP_OPS_EXE.SSE_PACKED
|
|
10.80 FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE
|
|
11.01 SIMD_FP_256.PACKED_SINGLE
|
|
11.02 SIMD_FP_256.PACKED_DOUBLE
|
|
14.01 ARITH.FPU_DIV_ACTIVE
|
|
17.01 INSTS_WRITTEN_TO_IQ.INSTS
|
|
24.01 L2_RQSTS.DEMAND_DATA_RD_HIT
|
|
24.03 L2_RQSTS.ALL_DEMAND_DATA_RD
|
|
24.04 L2_RQSTS.RFO_HITS
|
|
24.08 L2_RQSTS.RFO_MISS
|
|
24.0C L2_RQSTS.ALL_RFO
|
|
24.10 L2_RQSTS.CODE_RD_HIT
|
|
24.20 L2_RQSTS.CODE_RD_MISS
|
|
24.30 L2_RQSTS.ALL_CODE_RD
|
|
24.40 L2_RQSTS.PF_HIT
|
|
24.80 L2_RQSTS.PF_MISS
|
|
24.C0 L2_RQSTS.ALL_PF
|
|
27.01 L2_STORE_LOCK_RQSTS.MISS
|
|
27.04 L2_STORE_LOCK_RQSTS.HIT_E
|
|
27.08 L2_STORE_LOCK_RQSTS.HIT_M
|
|
27.0F L2_STORE_LOCK_RQSTS.ALL
|
|
28.01 L2_L1D_WB_RQSTS.MISS
|
|
28.02 L2_L1D_WB_RQSTS.HIT_S
|
|
28.04 L2_L1D_WB_RQSTS.HIT_E
|
|
28.08 L2_L1D_WB_RQSTS.HIT_M
|
|
28.0F L2_L1D_WB_RQSTS.ALL
|
|
2E.4F LONGEST_LAT_CACHE.REFERENCE
|
|
2E.41 LONGEST_LAT_CACHE.MISS
|
|
3C.00 CPU_CLK_UNHALTED.THREAD_P
|
|
3C.01 CPU_CLK_THREAD_UNHALTED.REF_XCLK
|
|
48.01.CTR=2 L1D_PEND_MISS.PENDING
|
|
49.01 DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
|
|
49.02 DTLB_STORE_MISSES.WALK_COMPLETED
|
|
49.04 DTLB_STORE_MISSES.WALK_DURATION
|
|
49.10 DTLB_STORE_MISSES.STLB_HIT
|
|
4C.01 LOAD_HIT_PRE.SW_PF
|
|
4C.02 LOAD_HIT_PRE.HW_PF
|
|
4E.02 HW_PRE_REQ.DL1_MISS
|
|
51.01 L1D.REPLACEMENT
|
|
51.02 L1D.ALLOCATED_IN_M
|
|
51.04 L1D.EVICTION
|
|
51.08 L1D.ALL_M_REPLACEMENT
|
|
59.20 PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP
|
|
59.40 PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW
|
|
59.80 PARTIAL_RAT_STALLS.MUL_SINGLE_UOP
|
|
5B.0C RESOURCE_STALLS2.ALL_FL_EMPTY
|
|
5B.0F RESOURCE_STALLS2.ALL_PRF_CONTROL
|
|
5B.40 RESOURCE_STALLS2.BOB_FULL
|
|
5B.4F RESOURCE_STALLS2.OOO_RSRC
|
|
5C.01 CPL_CYCLES.RING0
|
|
5C.02 CPL_CYCLES.RING123
|
|
5E.01 RS_EVENTS.EMPTY_CYCLES
|
|
60.01 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
|
|
60.04 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
|
|
60.08 OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
|
|
63.01 LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
|
|
63.02 LOCK_CYCLES.CACHE_LOCK_DURATION
|
|
79.02 IDQ.EMPTY
|
|
79.04 IDQ.MITE_UOPS
|
|
79.08 IDQ.DSB_UOPS
|
|
79.10 IDQ.MS_DSB_UOPS
|
|
79.20 IDQ.MS_MITE_UOPS
|
|
79.30 IDQ.MS_UOPS
|
|
80.02 ICACHE.MISSES
|
|
85.01 ITLB_MISSES.MISS_CAUSES_A_WALK
|
|
85.02 ITLB_MISSES.WALK_COMPLETED
|
|
85.04 ITLB_MISSES.WALK_DURATION
|
|
85.10 ITLB_MISSES.STLB_HIT
|
|
87.01 ILD_STALL.LCP
|
|
87.04 ILD_STALL.IQ_FULL
|
|
88.41 BR_INST_EXEC.NONTAKEN_CONDITIONAL
|
|
88.81 BR_INST_EXEC.TAKEN_CONDITIONAL
|
|
88.82 BR_INST_EXEC.TAKEN_DIRECT_JUMP
|
|
88.84 BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET
|
|
88.88 BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN
|
|
88.90 BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL
|
|
88.A0 BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL
|
|
88.C1 BR_INST_EXEC.ALL_CONDITIONAL
|
|
88.C2 BR_INST_EXEC.ALL_DIRECT_JUMP
|
|
88.C4 BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET
|
|
88.C8 BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN
|
|
88.D0 BR_INST_EXEC.ALL_NEAR_CALL
|
|
88.FF BR_INST_EXEC.ALL_BRANCHES
|
|
89.41 BR_MISP_EXEC.NONTAKEN_CONDITIONAL
|
|
89.81 BR_MISP_EXEC.TAKEN_CONDITIONAL
|
|
89.84 BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET
|
|
89.88 BR_MISP_EXEC.TAKEN_RETURN_NEAR
|
|
89.90 BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL
|
|
89.A0 BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL
|
|
89.C1 BR_MISP_EXEC.ALL_CONDITIONAL
|
|
89.C4 BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET
|
|
89.D0 BR_MISP_EXEC.ALL_NEAR_CALL
|
|
89.FF BR_MISP_EXEC.ALL_BRANCHES
|
|
9C.01 IDQ_UOPS_NOT_DELIVERED.CORE
|
|
A1.01 UOPS_DISPATCHED_PORT.PORT_0
|
|
A1.02 UOPS_DISPATCHED_PORT.PORT_1
|
|
A1.0C UOPS_DISPATCHED_PORT.PORT_2
|
|
A1.30 UOPS_DISPATCHED_PORT.PORT_3
|
|
A1.40 UOPS_DISPATCHED_PORT.PORT_4
|
|
A1.80 UOPS_DISPATCHED_PORT.PORT_5
|
|
A2.01 RESOURCE_STALLS.ANY
|
|
A2.02 RESOURCE_STALLS.LB
|
|
A2.04 RESOURCE_STALLS.RS
|
|
A2.08 RESOURCE_STALLS.SB
|
|
A2.10 RESOURCE_STALLS.ROB
|
|
A2.20 RESOURCE_STALLS.FCSW
|
|
A3.01 CYCLE_ACTIVITY.CYCLES_L2_PENDING
|
|
A3.02.CTR=2 CYCLE_ACTIVITY.CYCLES_L1D_PENDING
|
|
A3.04 CYCLE_ACTIVITY.CYCLES_NO_DISPATCH
|
|
A3.05 CYCLE_ACTIVITY.STALL_CYCLES_L2_PENDING
|
|
A3.06.CTR=2 CYCLE_ACTIVITY.STALL_CYCLES_L1D_PENDING
|
|
A8.01 LSD.UOPS
|
|
AB.01 DSB2MITE_SWITCHES.COUNT
|
|
AB.02 DSB2MITE_SWITCHES.PENALTY_CYCLES
|
|
AC.02 DSB_FILL.OTHER_CANCEL
|
|
AC.08 DSB_FILL.EXCEED_DSB_LINES
|
|
AE.01 ITLB.ITLB_FLUSH
|
|
B0.01 OFFCORE_REQUESTS.DEMAND_DATA_RD
|
|
B0.04 OFFCORE_REQUESTS.DEMAND_RFO
|
|
B0.08 OFFCORE_REQUESTS.ALL_DATA_RD
|
|
B1.01 UOPS_DISPATCHED.THREAD
|
|
B1.02 UOPS_DISPATCHED.CORE
|
|
B2.01 OFFCORE_REQUESTS_BUFFER.SQ_FULL
|
|
B6.01 AGU_BYPASS_CANCEL.COUNT
|
|
B7.01.CTR=0.MSR_RSP0=0x10001 OFF_CORE_RESPONSE_0.DMND_DATA_RD
|
|
B7.01.CTR=0.MSR_RSP0=0x10002 OFF_CORE_RESPONSE_0.DMND_RFO
|
|
B7.01.CTR=0.MSR_RSP0=0x10004 OFF_CORE_RESPONSE_0.DMND_IFETCH
|
|
B7.01.CTR=0.MSR_RSP0=0x10008 OFF_CORE_RESPONSE_0.WB
|
|
B7.01.CTR=0.MSR_RSP0=0x10010 OFF_CORE_RESPONSE_0.PF_DATA_RD
|
|
B7.01.CTR=0.MSR_RSP0=0x10020 OFF_CORE_RESPONSE_0.PF_RFO
|
|
B7.01.CTR=0.MSR_RSP0=0x10040 OFF_CORE_RESPONSE_0.PF_IFETCH
|
|
B7.01.CTR=0.MSR_RSP0=0x10080 OFF_CORE_RESPONSE_0.PF_LLC_DATA_RD
|
|
B7.01.CTR=0.MSR_RSP0=0x10100 OFF_CORE_RESPONSE_0.PF_LLC_RFO
|
|
B7.01.CTR=0.MSR_RSP0=0x10200 OFF_CORE_RESPONSE_0.PF_LLC_IFETCH
|
|
B7.01.CTR=0.MSR_RSP0=0x10400 OFF_CORE_RESPONSE_0.BUS_LOCKS
|
|
B7.01.CTR=0.MSR_RSP0=0x10800 OFF_CORE_RESPONSE_0.STRM_ST
|
|
B7.01.CTR=0.MSR_RSP0=0x18000 OFF_CORE_RESPONSE_0.OTHER
|
|
BB.01.CTR=1.MSR_RSP1=0x10001 OFF_CORE_RESPONSE_1.DMND_DATA_RD
|
|
BB.01.CTR=1.MSR_RSP1=0x10002 OFF_CORE_RESPONSE_1.DMND_RFO
|
|
BB.01.CTR=1.MSR_RSP1=0x10004 OFF_CORE_RESPONSE_1.DMND_IFETCH
|
|
BB.01.CTR=1.MSR_RSP1=0x10008 OFF_CORE_RESPONSE_1.WB
|
|
BB.01.CTR=1.MSR_RSP1=0x10010 OFF_CORE_RESPONSE_1.PF_DATA_RD
|
|
BB.01.CTR=1.MSR_RSP1=0x10020 OFF_CORE_RESPONSE_1.PF_RFO
|
|
BB.01.CTR=1.MSR_RSP1=0x10040 OFF_CORE_RESPONSE_1.PF_IFETCH
|
|
BB.01.CTR=1.MSR_RSP1=0x10080 OFF_CORE_RESPONSE_1.PF_LLC_DATA_RD
|
|
BB.01.CTR=1.MSR_RSP1=0x10100 OFF_CORE_RESPONSE_1.PF_LLC_RFO
|
|
BB.01.CTR=1.MSR_RSP1=0x10200 OFF_CORE_RESPONSE_1.PF_LLC_IFETCH
|
|
BB.01.CTR=1.MSR_RSP1=0x10400 OFF_CORE_RESPONSE_1.BUS_LOCKS
|
|
BB.01.CTR=1.MSR_RSP1=0x10800 OFF_CORE_RESPONSE_1.STRM_ST
|
|
BB.01.CTR=1.MSR_RSP1=0x18000 OFF_CORE_RESPONSE_1.OTHER
|
|
BD.01 TLB_FLUSH.DTLB_THREAD
|
|
BD.20 TLB_FLUSH.STLB_ANY
|
|
BF.05.CMSK=1 L1D_BLOCKS.BANK_CONFLICT_CYCLES
|
|
C0.00 INST_RETIRED.ANY_P
|
|
C0.01.CTR=1 INST_RETIRED.PREC_DIST
|
|
C1.02 OTHER_ASSISTS.ITLB_MISS_RETIRED
|
|
C1.08 OTHER_ASSISTS.AVX_STORE
|
|
C1.10 OTHER_ASSISTS.AVX_TO_SSE
|
|
C1.20 OTHER_ASSISTS.SSE_TO_AVX
|
|
C2.01 UOPS_RETIRED.ALL
|
|
C2.02 UOPS_RETIRED.RETIRE_SLOTS
|
|
C3.02 MACHINE_CLEARS.MEMORY_ORDERING
|
|
C3.04 MACHINE_CLEARS.SMC
|
|
C3.20 MACHINE_CLEARS.MASKMOV
|
|
C4.00 BR_INST_RETIRED.ALL_BRANCHES
|
|
C4.01 BR_INST_RETIRED.CONDITIONAL
|
|
C4.02 BR_INST_RETIRED.NEAR_CALL
|
|
C4.04 BR_INST_RETIRED.ALL_BRANCHES
|
|
C4.08 BR_INST_RETIRED.NEAR_RETURN
|
|
C4.10 BR_INST_RETIRED.NOT_TAKEN
|
|
C4.20 BR_INST_RETIRED.NEAR_TAKEN
|
|
C4.40 BR_INST_RETIRED.FAR_BRANCH
|
|
C5.00 BR_MISP_RETIRED.ALL_BRANCHES
|
|
C5.01 BR_MISP_RETIRED.CONDITIONAL
|
|
C5.02 BR_MISP_RETIRED.NEAR_CALL
|
|
C5.04 BR_MISP_RETIRED.ALL_BRANCHES
|
|
C5.10 BR_MISP_RETIRED.NOT_TAKEN
|
|
C5.20 BR_MISP_RETIRED.TAKEN
|
|
CA.02 FP_ASSIST.X87_OUTPUT
|
|
CA.04 FP_ASSIST.X87_INPUT
|
|
CA.08 FP_ASSIST.SIMD_OUTPUT
|
|
CA.10 FP_ASSIST.SIMD_INPUT
|
|
CA.1E FP_ASSIST.ANY
|
|
CC.20 ROB_MISC_EVENTS.LBR_INSERTS
|
|
CD.01.CTR=3.MSR_3F6H=10 MEM_TRANS_RETIRED.LOAD_LATENCY
|
|
CD.02.CTR=3 MEM_TRANS_RETIRED.PRECISE_STORE
|
|
D0.11 MEM_UOPS_RETIRED.STLB_MISS_LOADS
|
|
D0.12 MEM_UOPS_RETIRED.STLB_MISS_STORES
|
|
D0.21 MEM_UOPS_RETIRED.LOCK_LOADS
|
|
D0.41 MEM_UOPS_RETIRED.SPLIT_LOADS
|
|
D0.42 MEM_UOPS_RETIRED.SPLIT_STORES
|
|
D0.81 MEM_UOPS_RETIRED.ALL_LOADS
|
|
D0.82 MEM_UOPS_RETIRED.ALL_STORES
|
|
D1.01 MEM_LOAD_UOPS_RETIRED.L1_HIT
|
|
D1.02 MEM_LOAD_UOPS_RETIRED.L2_HIT
|
|
D1.04 MEM_LOAD_UOPS_RETIRED.LLC_HIT
|
|
D1.20 MEM_LOAD_UOPS_RETIRED.LLC_MISS
|
|
D1.40 MEM_LOAD_UOPS_RETIRED.HIT_LFB
|
|
D2.01 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
|
|
D2.02 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
|
|
D2.04 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
|
|
D2.08 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
|
|
E6.01 BACLEARS.ANY
|
|
F0.01 L2_TRANS.DEMAND_DATA_RD
|
|
F0.02 L2_TRANS.RFO
|
|
F0.04 L2_TRANS.CODE_RD
|
|
F0.08 L2_TRANS.ALL_PF
|
|
F0.10 L2_TRANS.L1D_WB
|
|
F0.20 L2_TRANS.L2_FILL
|
|
F0.40 L2_TRANS.L2_WB
|
|
F0.80 L2_TRANS.ALL_REQUESTS
|
|
F1.01 L2_LINES_IN.I
|
|
F1.02 L2_LINES_IN.S
|
|
F1.04 L2_LINES_IN.E
|
|
F1.07 L2_LINES_IN.ALL
|
|
F2.01 L2_LINES_OUT.DEMAND_CLEAN
|
|
F2.02 L2_LINES_OUT.DEMAND_DIRTY
|
|
F2.04 L2_LINES_OUT.PF_CLEAN
|
|
F2.08 L2_LINES_OUT.PF_DIRTY
|
|
F2.0A L2_LINES_OUT.DIRTY_ALL
|
|
F4.10 SQ_MISC.SPLIT_LOCK |