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19 lines
675 B
Plaintext
19 lines
675 B
Plaintext
# Performance monitoring events for processors based on the Westmere microarchitecture.
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# Applies to processors with DisplayFamily_DisplayModel of 06_25H and 06_2CH.
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# See Table 19-22 of Intel's "System Programming Guide" (Jan. 2019)
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0E.01 UOPS_ISSUED.ANY
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0E.02 UOPS_ISSUED.FUSED
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C2.01 UOPS_RETIRED.ANY
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B1.01 UOPS_EXECUTED.PORT0
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B1.02 UOPS_EXECUTED.PORT1
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B1.04 UOPS_EXECUTED.PORT2_CORE
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B1.08 UOPS_EXECUTED.PORT3_CORE
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B1.10 UOPS_EXECUTED.PORT4_CORE
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B1.20 UOPS_EXECUTED.PORT5
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C4.00 BR_INST_RETIRED.ALL_BRANCHES
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C5.04 BR_MISP_RETIRED.ALL_BRANCHES
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CB.01 MEM_LOAD_RETIRED.L1D_HIT
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CB.02 MEM_LOAD_RETIRED.L2_HIT
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CB.04 MEM_LOAD_RETIRED.L3_UNSHARED_HIT
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CB.10 MEM_LOAD_RETIRED.L3_MISS |