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DB update
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@@ -24,7 +24,7 @@ port_model_scheme: |
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| 36 | | 36 | | 36 | | 36 | | 48 | | 24 | | 26 | | 16 | | 12 | | 28 | | 28 |
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+------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+
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0 |FP0 1 |FP1 2 |FP2 3 |FP3 4 |D0 5 |D1 6 |D2 7 |D3 8 |INT0 9 |INT1 10 |INT2 11 |INT3 12 |INT4 13 |INT5
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\/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/
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\/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/
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+------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+
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| ALU | | ALU | | ALU | | ALU | | DV | | LD | | ST | | LD | | LD | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU |
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+------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+
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@@ -37,15 +37,15 @@ port_model_scheme: |
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+------+ +------+ +------+ +------+ +------+ +------+
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| FCSEL| | FCSEL| | FLAGS| | FLAGS| |MOV FP| silly | FMA |
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+------+ +------+ +------+ +------+ +------+ +------+
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+------+ +------+
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| 2INT | | 2INT |
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+------+ +------+
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+------+
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| RCP |
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+------+
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+------+
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| SHA |
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+------+
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+------+ +------+
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| 2INT | | 2INT |
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+------+ +------+
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+------+
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| RCP |
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+------+
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+------+
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| SHA |
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+------+
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instruction_forms:
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- name: [adc, adcs]
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operands:
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@@ -105,7 +105,7 @@ instruction_forms:
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- name: adds
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operands:
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- class: register
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prefix: '*'
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prefix: '*'
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- class: register
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prefix: '*'
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- class: register
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@@ -116,7 +116,7 @@ instruction_forms:
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- name: adds
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operands:
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- class: register
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prefix: '*'
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prefix: '*'
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- class: register
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prefix: '*'
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- class: immediate
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@@ -127,7 +127,7 @@ instruction_forms:
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- name: adr
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operands:
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- class: register
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prefix: '*'
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prefix: '*'
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- class: identifier
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throughput: 0.5
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latency: ~ # 1*p89
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@@ -1521,7 +1521,7 @@ instruction_forms:
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throughput: 0.16666666
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latency: ~ # 1*p89,10,11,12,13
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port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
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- name: [orn, orr]
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- name: [orn, orr]
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operands:
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- class: register
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prefix: x
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@@ -1532,7 +1532,7 @@ instruction_forms:
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throughput: 0.2
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latency: 1.0 # 1*p89,10,12,13
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port_pressure: [[1, ['8', '9', '10', '12', '13']]]
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- name: [orn, orr]
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- name: [orn, orr]
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operands:
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- class: register
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prefix: x
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@@ -1543,7 +1543,7 @@ instruction_forms:
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throughput: 0.16666666
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latency: 1.0 # 1*p89,10,11,12,13
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port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
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- name: [orn, orr]
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- name: [orn, orr]
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operands:
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- class: register
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prefix: w
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@@ -1554,7 +1554,7 @@ instruction_forms:
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throughput: 0.2
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latency: 1.0 # 1*p89,10,12,13
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port_pressure: [[1, ['8', '9', '10', '12', '13']]]
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- name: [orn, orr]
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- name: [orn, orr]
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operands:
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- class: register
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prefix: w
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@@ -1596,8 +1596,8 @@ instruction_forms:
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latency: ~
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port_pressure: []
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- name: ret
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operands:
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- class: identifier
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operands:
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- class: identifier
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throughput: 0.0
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latency: ~
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port_pressure: []
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@@ -1650,7 +1650,7 @@ instruction_forms:
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- name: [scvtf, ucvtf]
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operands:
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- class: register
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prefix: s
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prefix: s
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- class: register
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prefix: w
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throughput: 0.33333333
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@@ -1659,7 +1659,7 @@ instruction_forms:
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- name: [scvtf, ucvtf]
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operands:
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- class: register
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prefix: d
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prefix: d
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- class: register
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prefix: x
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throughput: 0.33333333
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@@ -1668,7 +1668,7 @@ instruction_forms:
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- name: [scvtf, ucvtf]
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operands:
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- class: register
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prefix: d
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prefix: d
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- class: register
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prefix: x
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- class: immediate
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@@ -1679,7 +1679,7 @@ instruction_forms:
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- name: [scvtf, ucvtf]
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operands:
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- class: register
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prefix: s
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prefix: s
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- class: register
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prefix: w
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- class: immediate
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@@ -2831,9 +2831,9 @@ instruction_forms:
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prefix: "*"
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- class: register
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prefix: "*"
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- class: immediate
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- class: immediate
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imd: int
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- class: immediate
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- class: immediate
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imd: int
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throughput: 0.16666666
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latency: 1.0 # 1*p89,10,11,12,13
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@@ -2912,7 +2912,7 @@ instruction_forms:
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prefix: s
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- class: immediate
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imd: int
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- class: condition
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- class: condition
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ccode: "*"
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throughput: 1.0
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latency: 1.0 # 1*p3
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@@ -3617,7 +3617,7 @@ instruction_forms:
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width: '*'
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throughput: 0.25
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latency: 2.0 # 1*p0123
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port_pressure: [[1, '0123']]
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port_pressure: [[1, '0123']]
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- name: [fmla, fmls]
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operands:
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- class: register
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1017
osaca/data/spr.yml
1017
osaca/data/spr.yml
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Load Diff
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