mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-07-21 12:41:05 +02:00
more black formatting
This commit is contained in:
JanLJL
@@ -43,7 +43,7 @@ class TestParserX86Intel(unittest.TestCase):
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self.assertEqual(self._get_label(self.parser, "$$B1?10:")[0].name, "$$B1?10")
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self.assertEqual(
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self._get_label(self.parser, "$LN9:\tcall\t__CheckForDebuggerJustMyCode")[0].name,
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"$LN9"
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"$LN9",
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)
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self.assertEqual(
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self._get_label(self.parser, "$LN9:\tcall\t__CheckForDebuggerJustMyCode")[1],
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@@ -57,28 +57,34 @@ class TestParserX86Intel(unittest.TestCase):
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label_id=None,
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line=None,
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line_number=None,
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)
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),
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)
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def test_directive_parser(self):
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self.assertEqual(self._get_directive(self.parser, "\t.allocstack 16")[0],
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DirectiveOperand(name=".allocstack",
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parameters=["16"]))
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self.assertEqual(self._get_directive(self.parser, "INCLUDELIB MSVCRTD")[0],
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DirectiveOperand(name="INCLUDELIB",
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parameters=["MSVCRTD"]))
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self.assertEqual(self._get_directive(self.parser, "msvcjmc\tSEGMENT")[0],
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DirectiveOperand(name="SEGMENT",
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parameters=["msvcjmc"]))
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self.assertEqual(self._get_directive(self.parser, "EXTRN\t_RTC_InitBase:PROC")[0],
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DirectiveOperand(name="EXTRN",
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parameters=["_RTC_InitBase:PROC"]))
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self.assertEqual(self._get_directive(self.parser, "$pdata$kernel DD imagerel $LN9")[0],
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DirectiveOperand(name="DD",
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parameters=["$pdata$kernel", "imagerel", "$LN9"]))
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self.assertEqual(self._get_directive(self.parser, "repeat$ = 320")[0],
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DirectiveOperand(name="=",
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parameters=["repeat$", "320"]))
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self.assertEqual(
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self._get_directive(self.parser, "\t.allocstack 16")[0],
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DirectiveOperand(name=".allocstack", parameters=["16"]),
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)
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self.assertEqual(
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self._get_directive(self.parser, "INCLUDELIB MSVCRTD")[0],
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DirectiveOperand(name="INCLUDELIB", parameters=["MSVCRTD"]),
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)
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self.assertEqual(
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self._get_directive(self.parser, "msvcjmc\tSEGMENT")[0],
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DirectiveOperand(name="SEGMENT", parameters=["msvcjmc"]),
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)
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self.assertEqual(
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self._get_directive(self.parser, "EXTRN\t_RTC_InitBase:PROC")[0],
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DirectiveOperand(name="EXTRN", parameters=["_RTC_InitBase:PROC"]),
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)
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self.assertEqual(
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self._get_directive(self.parser, "$pdata$kernel DD imagerel $LN9")[0],
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DirectiveOperand(name="DD", parameters=["$pdata$kernel", "imagerel", "$LN9"]),
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)
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self.assertEqual(
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self._get_directive(self.parser, "repeat$ = 320")[0],
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DirectiveOperand(name="=", parameters=["repeat$", "320"]),
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)
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def test_parse_instruction(self):
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instr1 = "\tsub\trsp, 296\t\t\t\t; 00000128H"
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@@ -110,93 +116,93 @@ class TestParserX86Intel(unittest.TestCase):
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parsed_13 = self.parser.parse_instruction(instr13)
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self.assertEqual(parsed_1.mnemonic, "sub")
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self.assertEqual(parsed_1.operands[0],
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RegisterOperand(name="RSP"))
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self.assertEqual(parsed_1.operands[1],
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ImmediateOperand(value=296))
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self.assertEqual(parsed_1.operands[0], RegisterOperand(name="RSP"))
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self.assertEqual(parsed_1.operands[1], ImmediateOperand(value=296))
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self.assertEqual(parsed_1.comment, "00000128H")
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self.assertEqual(parsed_2.mnemonic, "fst")
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self.assertEqual(parsed_2.operands[0],
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RegisterOperand(name="ST(3)"))
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self.assertEqual(parsed_2.operands[0], RegisterOperand(name="ST(3)"))
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self.assertEqual(parsed_2.comment, "Good ol' x87.")
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self.assertEqual(parsed_3.mnemonic, "mulsd")
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self.assertEqual(parsed_3.operands[0],
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RegisterOperand(name="XMM0"))
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self.assertEqual(parsed_3.operands[1],
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MemoryOperand(base=RegisterOperand(name="RDX"),
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index=RegisterOperand(name="RCX"),
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scale=8))
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self.assertEqual(parsed_3.operands[0], RegisterOperand(name="XMM0"))
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self.assertEqual(
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parsed_3.operands[1],
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MemoryOperand(
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base=RegisterOperand(name="RDX"), index=RegisterOperand(name="RCX"), scale=8
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),
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)
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self.assertEqual(parsed_4.mnemonic, "mov")
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self.assertEqual(parsed_4.operands[0],
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RegisterOperand(name="EAX"))
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self.assertEqual(parsed_4.operands[0], RegisterOperand(name="EAX"))
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self.assertEqual(
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parsed_4.operands[1],
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MemoryOperand(
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offset=ImmediateOperand(identifier="cur_elements$", value=104),
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base=RegisterOperand(name="RBP")
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)
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base=RegisterOperand(name="RBP"),
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),
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)
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self.assertEqual(parsed_5.mnemonic, "mov")
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self.assertEqual(parsed_5.operands[0],
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MemoryOperand(offset=ImmediateOperand(value=24),
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base=RegisterOperand(name="RSP")))
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self.assertEqual(parsed_5.operands[1],
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RegisterOperand(name="R8"))
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self.assertEqual(
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parsed_5.operands[0],
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MemoryOperand(offset=ImmediateOperand(value=24), base=RegisterOperand(name="RSP")),
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)
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self.assertEqual(parsed_5.operands[1], RegisterOperand(name="R8"))
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self.assertEqual(parsed_6.mnemonic, "jmp")
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self.assertEqual(parsed_6.operands[0],
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LabelOperand(name="$LN2@kernel"))
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self.assertEqual(parsed_6.operands[0], LabelOperand(name="$LN2@kernel"))
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self.assertEqual(parsed_7.mnemonic, "lea")
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self.assertEqual(parsed_7.operands[0],
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RegisterOperand(name="RCX"))
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self.assertEqual(parsed_7.operands[1],
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MemoryOperand(offset=IdentifierOperand(name="__FAC6D534_triad@c")))
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self.assertEqual(parsed_7.operands[0], RegisterOperand(name="RCX"))
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self.assertEqual(
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parsed_7.operands[1],
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MemoryOperand(offset=IdentifierOperand(name="__FAC6D534_triad@c")),
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)
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self.assertEqual(parsed_8.mnemonic, "mov")
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self.assertEqual(parsed_8.operands[0],
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MemoryOperand(
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base=RegisterOperand(name="GS"),
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offset=ImmediateOperand(value=111)))
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self.assertEqual(parsed_8.operands[1],
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RegisterOperand(name="AL"))
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self.assertEqual(
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parsed_8.operands[0],
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MemoryOperand(base=RegisterOperand(name="GS"), offset=ImmediateOperand(value=111)),
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)
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self.assertEqual(parsed_8.operands[1], RegisterOperand(name="AL"))
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self.assertEqual(parsed_9.mnemonic, "lea")
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self.assertEqual(parsed_9.operands[0],
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RegisterOperand(name="R8"))
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self.assertEqual(parsed_9.operands[1],
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MemoryOperand(base=None,
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index=RegisterOperand(name="R8"),
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scale=4))
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self.assertEqual(parsed_9.operands[0], RegisterOperand(name="R8"))
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self.assertEqual(
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parsed_9.operands[1],
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MemoryOperand(base=None, index=RegisterOperand(name="R8"), scale=4),
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)
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self.assertEqual(parsed_10.mnemonic, "movsd")
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self.assertEqual(parsed_10.operands[0],
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RegisterOperand(name="XMM1"))
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self.assertEqual(parsed_10.operands[1],
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MemoryOperand(offset=IdentifierOperand(name="boost@@XZ@4V456@A",
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offset=ImmediateOperand(value=16))))
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self.assertEqual(parsed_10.operands[0], RegisterOperand(name="XMM1"))
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self.assertEqual(
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parsed_10.operands[1],
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MemoryOperand(
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offset=IdentifierOperand(
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name="boost@@XZ@4V456@A", offset=ImmediateOperand(value=16)
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)
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),
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)
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self.assertEqual(parsed_11.mnemonic, "lea")
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self.assertEqual(parsed_11.operands[0],
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RegisterOperand(name="RCX"))
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self.assertEqual(parsed_11.operands[1],
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MemoryOperand(offset=IdentifierOperand(name="??_R0N@8",
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offset=ImmediateOperand(value=8))))
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self.assertEqual(parsed_11.operands[0], RegisterOperand(name="RCX"))
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self.assertEqual(
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parsed_11.operands[1],
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MemoryOperand(
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offset=IdentifierOperand(name="??_R0N@8", offset=ImmediateOperand(value=8))
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),
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)
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self.assertEqual(parsed_12.mnemonic, "vfmadd213sd")
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self.assertEqual(parsed_12.operands[0],
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RegisterOperand(name="XMM0"))
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self.assertEqual(parsed_12.operands[1],
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RegisterOperand(name="XMM1"))
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self.assertEqual(parsed_12.operands[2],
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MemoryOperand(offset=IdentifierOperand(name="__real@bfc5555555555555")))
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self.assertEqual(parsed_12.operands[0], RegisterOperand(name="XMM0"))
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self.assertEqual(parsed_12.operands[1], RegisterOperand(name="XMM1"))
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self.assertEqual(
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parsed_12.operands[2],
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MemoryOperand(offset=IdentifierOperand(name="__real@bfc5555555555555")),
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)
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self.assertEqual(parsed_13.mnemonic, "jmp")
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self.assertEqual(parsed_13.operands[0],
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IdentifierOperand(name="$LN18@operator"))
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self.assertEqual(parsed_13.operands[0], IdentifierOperand(name="$LN18@operator"))
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def test_parse_line(self):
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line_comment = "; -- Begin main"
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@@ -257,63 +263,85 @@ class TestParserX86Intel(unittest.TestCase):
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operands=[
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MemoryOperand(
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base=RegisterOperand("RBP"),
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offset=ImmediateOperand(value=4, identifier="r$1")
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offset=ImmediateOperand(value=4, identifier="r$1"),
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),
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ImmediateOperand(value=0)
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ImmediateOperand(value=0),
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],
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line="\tmov\tDWORD PTR r$1[rbp], 0",
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line_number=73
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)
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line_number=73,
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),
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)
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# Check a few lines to make sure that we produced something reasonable.
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self.assertEqual(parsed[60],
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InstructionForm(mnemonic="mov",
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operands=[MemoryOperand(base=RegisterOperand("RSP"),
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offset=ImmediateOperand(value=8)),
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RegisterOperand(name="RCX")],
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line="\tmov\tQWORD PTR [rsp+8], rcx",
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line_number=64))
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self.assertEqual(parsed[120],
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InstructionForm(directive_id=DirectiveOperand(name="END"),
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line="END",
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line_number=124))
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self.assertEqual(
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parsed[60],
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InstructionForm(
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mnemonic="mov",
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operands=[
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MemoryOperand(base=RegisterOperand("RSP"), offset=ImmediateOperand(value=8)),
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RegisterOperand(name="RCX"),
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],
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line="\tmov\tQWORD PTR [rsp+8], rcx",
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line_number=64,
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),
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)
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self.assertEqual(
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parsed[120],
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InstructionForm(
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directive_id=DirectiveOperand(name="END"), line="END", line_number=124
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),
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)
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self.assertEqual(len(parsed), 121)
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def test_parse_file2(self):
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parsed = self.parser.parse_file(self.triad_iaca_code)
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self.assertEqual(parsed[0].line_number, 1)
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# Check a few lines to make sure that we produced something reasonable.
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self.assertEqual(parsed[68],
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InstructionForm(directive_id=DirectiveOperand(name="=",
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parameters=["s$", "88"]),
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line="s$ = 88",
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line_number=72))
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self.assertEqual(parsed[135],
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InstructionForm(directive_id=DirectiveOperand(name="END"),
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line="END",
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line_number=139))
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self.assertEqual(
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parsed[68],
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InstructionForm(
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directive_id=DirectiveOperand(name="=", parameters=["s$", "88"]),
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line="s$ = 88",
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line_number=72,
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),
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)
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self.assertEqual(
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parsed[135],
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InstructionForm(
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directive_id=DirectiveOperand(name="END"), line="END", line_number=139
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),
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)
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self.assertEqual(len(parsed), 136)
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def test_parse_file3(self):
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parsed = self.parser.parse_file(self.gs_icc_code)
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self.assertEqual(parsed[0].line_number, 1)
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# Check a few lines to make sure that we produced something reasonable.
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self.assertEqual(parsed[113],
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InstructionForm(mnemonic="vmovsd",
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operands=[RegisterOperand("XMM5"),
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MemoryOperand(base=RegisterOperand("R11"),
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index=RegisterOperand("R10"),
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scale=1,
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offset=ImmediateOperand(value=16))],
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comment_id="26.19",
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line=" vmovsd xmm5, QWORD PTR [16+r11+r10]"
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+ " #26.19",
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line_number=114))
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self.assertEqual(parsed[226],
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InstructionForm(directive_id=DirectiveOperand(name=".long",
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parameters=["681509"]),
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line=" .long 681509",
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line_number=227))
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self.assertEqual(
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parsed[113],
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InstructionForm(
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mnemonic="vmovsd",
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operands=[
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RegisterOperand("XMM5"),
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MemoryOperand(
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base=RegisterOperand("R11"),
|
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index=RegisterOperand("R10"),
|
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scale=1,
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offset=ImmediateOperand(value=16),
|
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),
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],
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comment_id="26.19",
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line=" vmovsd xmm5, QWORD PTR [16+r11+r10]" + " #26.19",
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line_number=114,
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),
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)
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self.assertEqual(
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parsed[226],
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InstructionForm(
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directive_id=DirectiveOperand(name=".long", parameters=["681509"]),
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line=" .long 681509",
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line_number=227,
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),
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)
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self.assertEqual(len(parsed), 227)
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def test_normalize_imd(self):
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@@ -342,9 +370,7 @@ class TestParserX86Intel(unittest.TestCase):
|
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##################
|
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def _get_comment(self, parser, comment):
|
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return " ".join(
|
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parser.process_operand(parser.comment.parseString(comment, parseAll=True))[
|
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"comment"
|
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]
|
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parser.process_operand(parser.comment.parseString(comment, parseAll=True))["comment"]
|
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)
|
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def _get_label(self, parser, label):
|
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|
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@@ -54,40 +54,31 @@ class TestSemanticTools(unittest.TestCase):
|
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with open(cls._find_file("kernel_aarch64_deps.s")) as f:
|
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cls.code_AArch64_deps = f.read()
|
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cls.kernel_x86 = reduce_to_section(
|
||||
cls.parser_x86_att.parse_file(cls.code_x86),
|
||||
cls.parser_x86_att
|
||||
cls.parser_x86_att.parse_file(cls.code_x86), cls.parser_x86_att
|
||||
)
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||||
cls.kernel_x86_memdep = reduce_to_section(
|
||||
cls.parser_x86_att.parse_file(cls.code_x86_memdep),
|
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cls.parser_x86_att
|
||||
cls.parser_x86_att.parse_file(cls.code_x86_memdep), cls.parser_x86_att
|
||||
)
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cls.kernel_x86_long_LCD = reduce_to_section(
|
||||
cls.parser_x86_att.parse_file(cls.code_x86_long_LCD),
|
||||
cls.parser_x86_att
|
||||
cls.parser_x86_att.parse_file(cls.code_x86_long_LCD), cls.parser_x86_att
|
||||
)
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cls.kernel_x86_intel = reduce_to_section(
|
||||
cls.parser_x86_intel.parse_file(cls.code_x86_intel),
|
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cls.parser_x86_intel
|
||||
cls.parser_x86_intel.parse_file(cls.code_x86_intel), cls.parser_x86_intel
|
||||
)
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cls.kernel_x86_intel_memdep = reduce_to_section(
|
||||
cls.parser_x86_intel.parse_file(cls.code_x86_intel_memdep),
|
||||
cls.parser_x86_intel
|
||||
cls.parser_x86_intel.parse_file(cls.code_x86_intel_memdep), cls.parser_x86_intel
|
||||
)
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||||
cls.kernel_AArch64 = reduce_to_section(
|
||||
cls.parser_AArch64.parse_file(cls.code_AArch64),
|
||||
cls.parser_AArch64
|
||||
cls.parser_AArch64.parse_file(cls.code_AArch64), cls.parser_AArch64
|
||||
)
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||||
cls.kernel_aarch64_memdep = reduce_to_section(
|
||||
cls.parser_AArch64.parse_file(cls.code_aarch64_memdep),
|
||||
cls.parser_AArch64
|
||||
cls.parser_AArch64.parse_file(cls.code_aarch64_memdep), cls.parser_AArch64
|
||||
)
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||||
cls.kernel_aarch64_SVE = reduce_to_section(
|
||||
cls.parser_AArch64.parse_file(cls.code_AArch64_SVE),
|
||||
cls.parser_AArch64
|
||||
cls.parser_AArch64.parse_file(cls.code_AArch64_SVE), cls.parser_AArch64
|
||||
)
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||||
cls.kernel_aarch64_deps = reduce_to_section(
|
||||
cls.parser_AArch64.parse_file(cls.code_AArch64_deps),
|
||||
cls.parser_AArch64
|
||||
cls.parser_AArch64.parse_file(cls.code_AArch64_deps), cls.parser_AArch64
|
||||
)
|
||||
|
||||
# set up machine models
|
||||
@@ -438,10 +429,7 @@ class TestSemanticTools(unittest.TestCase):
|
||||
# 5_______>9
|
||||
#
|
||||
dg = KernelDG(
|
||||
self.kernel_x86,
|
||||
self.parser_x86_att,
|
||||
self.machine_model_csx,
|
||||
self.semantics_csx
|
||||
self.kernel_x86, self.parser_x86_att, self.machine_model_csx, self.semantics_csx
|
||||
)
|
||||
self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg))
|
||||
self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=3))), 1)
|
||||
@@ -472,7 +460,7 @@ class TestSemanticTools(unittest.TestCase):
|
||||
self.kernel_x86_intel,
|
||||
self.parser_x86_intel,
|
||||
self.machine_model_csx,
|
||||
self.semantics_csx_intel
|
||||
self.semantics_csx_intel,
|
||||
)
|
||||
self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg))
|
||||
self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=3))), 1)
|
||||
@@ -589,10 +577,7 @@ class TestSemanticTools(unittest.TestCase):
|
||||
|
||||
def test_cyclic_dag(self):
|
||||
dg = KernelDG(
|
||||
self.kernel_x86,
|
||||
self.parser_x86_att,
|
||||
self.machine_model_csx,
|
||||
self.semantics_csx
|
||||
self.kernel_x86, self.parser_x86_att, self.machine_model_csx, self.semantics_csx
|
||||
)
|
||||
dg.dg.add_edge(100, 101, latency=1.0)
|
||||
dg.dg.add_edge(101, 102, latency=2.0)
|
||||
@@ -659,10 +644,7 @@ class TestSemanticTools(unittest.TestCase):
|
||||
lcd_id = "8"
|
||||
lcd_id2 = "5"
|
||||
dg = KernelDG(
|
||||
self.kernel_x86,
|
||||
self.parser_x86_att,
|
||||
self.machine_model_csx,
|
||||
self.semantics_csx
|
||||
self.kernel_x86, self.parser_x86_att, self.machine_model_csx, self.semantics_csx
|
||||
)
|
||||
lc_deps = dg.get_loopcarried_dependencies()
|
||||
# self.assertEqual(len(lc_deps), 2)
|
||||
@@ -695,7 +677,7 @@ class TestSemanticTools(unittest.TestCase):
|
||||
self.kernel_x86_intel,
|
||||
self.parser_x86_intel,
|
||||
self.machine_model_csx,
|
||||
self.semantics_csx_intel
|
||||
self.semantics_csx_intel,
|
||||
)
|
||||
lc_deps = dg.get_loopcarried_dependencies()
|
||||
# self.assertEqual(len(lc_deps), 2)
|
||||
@@ -804,14 +786,10 @@ class TestSemanticTools(unittest.TestCase):
|
||||
self.semantics_csx_intel.normalize_instruction_form(instr_form_w_c)
|
||||
self.semantics_csx_intel.assign_src_dst(instr_form_w_c)
|
||||
|
||||
instr_form_rw_ymm_1 = self.parser_x86_intel.parse_line(
|
||||
"vinsertf128 ymm1, ymm0, xmm1, 1"
|
||||
)
|
||||
instr_form_rw_ymm_1 = self.parser_x86_intel.parse_line("vinsertf128 ymm1, ymm0, xmm1, 1")
|
||||
self.semantics_csx_intel.normalize_instruction_form(instr_form_rw_ymm_1)
|
||||
self.semantics_csx_intel.assign_src_dst(instr_form_rw_ymm_1)
|
||||
instr_form_rw_ymm_2 = self.parser_x86_intel.parse_line(
|
||||
"vinsertf128 ymm1, ymm1, xmm0, 1"
|
||||
)
|
||||
instr_form_rw_ymm_2 = self.parser_x86_intel.parse_line("vinsertf128 ymm1, ymm1, xmm0, 1")
|
||||
self.semantics_csx_intel.normalize_instruction_form(instr_form_rw_ymm_2)
|
||||
self.semantics_csx_intel.assign_src_dst(instr_form_rw_ymm_2)
|
||||
instr_form_r_ymm = self.parser_x86_intel.parse_line("vmovapd ymm0, ymm1")
|
||||
|
||||
Reference in New Issue
Block a user