42 Commits

Author	SHA1	Message	Date
JanLJL	e8b78e4cc6	Merge branch 'master' into A64FX	2020-10-15 22:44:12 +02:00
Julian Hammer	748474cd81	added more cmp versions	2020-10-15 16:23:14 +02:00
JanLJL	93060eee43	Merge branch 'master' into A64FX	2020-07-13 14:41:49 +02:00
Cloud User	34e978d2ae	initial implementation of Neoverse N1 support	2020-06-30 20:28:57 +00:00
JanLJL	6294e2e9da	initial commit for trying to support a64fx	2020-06-26 05:20:40 +02:00
Julian Hammer	9624e6c109	closing cache file after dump	2020-03-24 15:20:49 +01:00
Julian Hammer	c5801cfe2f	closing cache file	2020-03-21 17:18:04 +01:00
JanLJL	1aa710f195	enhanced MachineModel to support mask/zeroing differentiation for instruction forms	2020-03-17 12:55:37 +01:00
JanLJL	17e7f0e0d8	more instruction forms and added wildcard support for registers in ISA DB	2020-03-12 15:07:51 +01:00
JanLJL	4e73e24b99	added documentation	2020-03-09 16:35:06 +01:00
Julian Hammer	0adde7b9fc	added ice lake abbreviation	2020-02-05 10:05:57 +01:00
JanLJL	421cf55af7	minor enhancements and bugfixes	2020-01-27 16:37:28 +01:00
JanLJL	02233f627e	added file caching for DBs	2020-01-22 15:07:46 +01:00
Julian Hammer	b2bb2cd003	small changes	2020-01-17 15:04:08 +01:00
JanLJL	c2d8742ac0	allows aliasing in uarch DB via list-name	2020-01-17 12:21:46 +01:00
JanLJL	5b1c984552	adjusted test due to hidden operand dependencies	2020-01-17 08:13:15 +01:00
JanLJL	cb100d118f	small bugfix for mm registers	2020-01-14 18:24:00 +01:00
JanLJL	b6572720af	enhanced for dynamic ST throughput combination	2020-01-14 10:49:47 +01:00
JanLJL	623c4ea113	added wildcard mode for mem addressing in ISA DB	2020-01-10 12:55:44 +01:00
JanLJL	bad230fa7b	enhanced dynamic combine of LD and arithmetic instr	2019-12-19 18:50:48 +01:00
JanLJL	b2b4aba0f3	added default load tp in new HW model	2019-12-18 16:58:34 +01:00
JanLJL	bbb004a2aa	added default load TP and relocation in identifier	2019-12-18 16:56:20 +01:00
JanLJL	d88617109f	changed from dict DB back to list DB for now	2019-12-16 18:25:27 +01:00
JanLJL	9d069c39d9	performance enhancement by removing unnecessary DB parsings	2019-12-02 15:39:59 +01:00
Julian Hammer	f18a48653f	FIX #46 untangled semantic and non-semantic operand info	2019-11-14 16:43:33 +01:00
Jan	af0c8fc953	Merge pull request #45 from RRZE-HPC/v3 ... ibench & asmbench interfaces	2019-10-24 14:45:12 +02:00
JanLJL	8b4acf0508	fixed last problems with ibench import	2019-10-24 12:38:26 +02:00
Julian Hammer	b1e4cb90a7	better formatting of load_throughput dump	2019-10-22 14:43:43 +02:00
JanLJL	d92523e133	changed DBs to new port_pressure structure	2019-10-16 10:06:47 +02:00
Julian Hammer	cb7cec20a8	working importer, better dumper	2019-10-15 12:22:49 +02:00
Julian Hammer	1c673382b4	work in progress	2019-10-14 17:08:40 +02:00
Julian Hammer	792bbb1166	removed some unnecessary file checks and fixed up test cases	2019-10-11 16:13:58 +02:00
JanLJL	625d814dce	new dynamic tp and lt values for LD instructions	2019-09-26 21:39:56 +02:00
JanLJL	f2eff01529	more tests and bugfixes	2019-08-29 16:36:14 +02:00
JanLJL	80e741d411	enhanced frontend and added hidable load port	2019-08-29 14:03:16 +02:00
JanLJL	df8a81bf4d	initial version of loop-carried dependencies checker	2019-08-23 19:01:20 +02:00
JanLJL	866397d6ae	finished DB sanity check and cleaned DBs	2019-08-13 18:13:41 +02:00
JanLJL	b09129eeb7	more tests for Arm	2019-08-09 11:01:08 +02:00
JanLJL	cb75bf52ab	first basic analysis version	2019-07-24 10:57:19 +02:00
JanLJL	a866500610	added DiGraph creation and more tests	2019-07-10 18:25:32 +02:00
JanLJL	75393f106c	finished refactoring for semanticsAppender, including first tests	2019-07-08 15:47:08 +02:00
JanLJL	03dff0013f	initial upload - not functional yet	2019-07-05 17:11:18 +02:00