Commit Graph

  • ebf76caa18 Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames dev/risc-v Metehan Dundar 2025-07-11 18:15:51 +02:00
  • 61b52dbf28 RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests Metehan Dundar 2025-06-30 00:28:52 +02:00
  • 480c0dcac0 Merge branch 'master' into dev/risc-v Metehan Dundar 2025-05-08 12:23:22 +02:00
  • aa3753d024 Add RISC-V vector add and triad benchmarks with corresponding Makefiles and assembly files Metehan Dundar 2025-05-08 11:57:06 +02:00
  • 33fd0a0352 Merge pull request #116 from eggrobin/graph-colouring master Jan 2025-03-31 11:38:23 +02:00
  • 2c4a545f3b Merge pull request #116 from eggrobin/graph-colouring Jan 2025-03-31 11:38:23 +02:00
  • a17e79a3a9 Merge pull request #115 from pleroy/Comisd Jan 2025-03-31 11:18:09 +02:00
  • 25bcf59789 Merge pull request #115 from pleroy/Comisd Jan 2025-03-31 11:18:09 +02:00
  • de0b1fde64 white on blue Robin Leroy 2025-01-02 03:06:14 +01:00
  • da2ce51446 white on blue Robin Leroy 2025-01-02 03:06:14 +01:00
  • d82bc8052b Less clever and more useful colouring Robin Leroy 2025-01-01 23:13:52 +01:00
  • 4526baa6ae Less clever and more useful colouring Robin Leroy 2025-01-01 23:13:52 +01:00
  • b854562a82 Improve dependency graph colouring Robin Leroy 2025-01-01 18:34:28 +01:00
  • 9040757e91 Improve dependency graph colouring Robin Leroy 2025-01-01 18:34:28 +01:00
  • 8c31c6ff77 Mark backward edges as backward so the graph is ordered like the code Robin Leroy 2025-01-01 04:03:09 +01:00
  • 638d938325 Mark backward edges as backward so the graph is ordered like the code Robin Leroy 2025-01-01 04:03:09 +01:00
  • e096cf4704 Don’t spam filled until dot breaks Robin Leroy 2025-01-01 03:55:51 +01:00
  • a4c6d84b0c Don’t spam filled until dot breaks Robin Leroy 2025-01-01 03:55:51 +01:00
  • 7d900fde38 Don’t run out of colours Robin Leroy 2024-12-30 21:48:15 +01:00
  • 034d192c57 Don’t run out of colours Robin Leroy 2024-12-30 21:48:15 +01:00
  • 28df996617 Moar colors. pleroy 2024-12-30 19:14:17 +01:00
  • ed263f696a Moar colors. pleroy 2024-12-30 19:14:17 +01:00
  • 1eb82a6f0a Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write. pleroy 2024-12-29 18:11:15 +01:00
  • 939089030b Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write. pleroy 2024-12-29 18:11:15 +01:00
  • b7e4acc905 ucomisd is like comisd Robin Leroy 2024-12-30 22:50:03 +01:00
  • d2b8b7771f ucomisd is like comisd Robin Leroy 2024-12-30 22:50:03 +01:00
  • b989145a36 Define comisd sources. pleroy 2024-12-30 19:55:20 +01:00
  • ea59056f94 Define comisd sources. pleroy 2024-12-30 19:55:20 +01:00
  • 9c97d32512 Merge pull request #114 from eggrobin/setmeow-jmeow Jan 2025-03-26 09:05:23 +01:00
  • ce0f78e441 Merge pull request #114 from eggrobin/setmeow-jmeow Jan 2025-03-26 09:05:23 +01:00
  • d782f06e84 Add RISC-V support and update version to 0.6.2 Metehan Dundar 2025-03-21 17:16:39 +01:00
  • 9e6373a013 Configure the dependencies of the jmeow instructions on flags Robin Leroy 2025-01-05 18:21:44 +01:00
  • 122f8a674b Configure the dependencies of the jmeow instructions on flags Robin Leroy 2025-01-05 18:21:44 +01:00
  • e99c3d935d Add the setmeow instructions Robin Leroy 2025-01-01 06:07:01 +01:00
  • 94f32c51a7 Add the setmeow instructions Robin Leroy 2025-01-01 06:07:01 +01:00
  • edb32b38ca use pypi version of kerncraft for GH Actions JanLJL 2025-03-19 14:36:49 +01:00
  • 734979521b use pypi version of kerncraft for GH Actions JanLJL 2025-03-19 14:36:49 +01:00
  • 2a231bf20b version bump v0.7.0 JanLJL 2025-03-17 10:28:06 +01:00
  • 1627f0e49d version bump JanLJL 2025-03-17 10:28:06 +01:00
  • fb8c8ec7db remove AT&T limitation JanLJL 2025-03-17 10:27:41 +01:00
  • 68252c86b9 remove AT&T limitation JanLJL 2025-03-17 10:27:41 +01:00
  • 2f069000e9 add syntax flag in README Jan 2025-03-17 10:26:50 +01:00
  • d4d84fa49e add syntax flag in README Jan 2025-03-17 10:26:50 +01:00
  • bdbcb18817 Merge pull request #112 from pleroy/Intel Jan 2025-03-17 10:20:40 +01:00
  • 2b838b7bdd Merge pull request #112 from pleroy/Intel Jan 2025-03-17 10:20:40 +01:00
  • 7930e4d704 take +- operator of offset/index in mem-addr into account JanLJL 2025-03-14 15:40:16 +01:00
  • 31f5912af6 take +- operator of offset/index in mem-addr into account JanLJL 2025-03-14 15:40:16 +01:00
  • 850f7edc6b RISCV.yml file has been updated. Metehan Dundar 2025-03-13 09:54:06 +01:00
  • d61330404b Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. pleroy 2025-03-12 22:26:38 +01:00
  • 732dd95810 Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. pleroy 2025-03-12 22:26:38 +01:00
  • 91da9a311a Upper case the argument to the --syntax flag, otherwise 'att' means 'intel' :-/ pleroy 2025-03-12 00:29:10 +01:00
  • f846f0ed7d Upper case the argument to the --syntax flag, otherwise 'att' means 'intel' :-/ pleroy 2025-03-12 00:29:10 +01:00
  • 0c201be10e Revert 62908f3b8f and fix a failure in tests.test_cli.TestCLI.test_without_arch while preserving the possibility to try more archs than the detected one. pleroy 2025-03-11 23:34:36 +01:00
  • e3910056cf Revert d772522400 and fix a failure in tests.test_cli.TestCLI.test_without_arch while preserving the possibility to try more archs than the detected one. pleroy 2025-03-11 23:34:36 +01:00
  • a75098c9f5 Add RISCV parser to test suite Metehan Dundar 2025-03-11 11:42:15 +01:00
  • 653c27135d Add initial support for RISC-V architecture and update relevant files Metehan Dundar 2025-03-11 05:10:03 +01:00
  • 2cf2bf5cec Merge branch 'master' into merge-branch JanLJL 2025-03-07 14:45:44 +01:00
  • ffb5f0eb55 Merge branch 'master' into merge-branch JanLJL 2025-03-07 14:45:44 +01:00
  • 4e3994fec1 added support for <Xd>! registers and [<Xd>]! mem addresses in Arm JanLJL 2025-03-07 11:49:14 +01:00
  • bcecabd911 added support for <Xd>! registers and [<Xd>]! mem addresses in Arm JanLJL 2025-03-07 11:49:14 +01:00
  • ff727223bb add setuptools to Install JanLJL 2025-03-05 13:19:09 +01:00
  • 022bd2997d add setuptools to Install JanLJL 2025-03-05 13:19:09 +01:00
  • 306abcf0a6 specify commit for kerncraft JanLJL 2025-03-05 12:54:55 +01:00
  • bec925d5aa specify commit for kerncraft JanLJL 2025-03-05 12:54:55 +01:00
  • 0b1ada14d0 undo unnecessary install JanLJL 2025-03-05 11:01:47 +01:00
  • 461bf0306f undo unnecessary install JanLJL 2025-03-05 11:01:47 +01:00
  • 81dfb0e6cb use local osaca version JanLJL 2025-03-05 11:00:08 +01:00
  • 585e2d6177 use local osaca version JanLJL 2025-03-05 11:00:08 +01:00
  • 796256fa13 more black formatting JanLJL 2025-03-05 10:40:18 +01:00
  • b7e5df0a08 more black formatting JanLJL 2025-03-05 10:40:18 +01:00
  • 99d0e0ffb6 install kerncraft from git repo JanLJL 2025-03-05 10:38:39 +01:00
  • 799acd5c20 install kerncraft from git repo JanLJL 2025-03-05 10:38:39 +01:00
  • 9c2f559983 black formatting JanLJL 2025-03-05 10:20:47 +01:00
  • 63f56e50b4 black formatting JanLJL 2025-03-05 10:20:47 +01:00
  • 02716e7b41 flake8 formatting JanLJL 2025-03-05 10:19:10 +01:00
  • fb7f1a289d flake8 formatting JanLJL 2025-03-05 10:19:10 +01:00
  • 5cd6b2cf9d renamed .asm files to .s for consistency JanLJL 2025-03-05 09:36:07 +01:00
  • a4939d1873 renamed .asm files to .s for consistency JanLJL 2025-03-05 09:36:07 +01:00
  • be3622ce86 bugfixes JanLJL 2025-03-04 17:46:37 +01:00
  • 4e6d37aa9f bugfixes JanLJL 2025-03-04 17:46:37 +01:00
  • 63774e65bc chmod +x JanLJL 2025-03-04 17:46:23 +01:00
  • 1c2e0f3921 chmod +x JanLJL 2025-03-04 17:46:23 +01:00
  • 796cfdc3b5 add test case for specific syntax parameter in get_asm_parser() JanLJL 2025-03-04 17:45:19 +01:00
  • 3de6097a06 add test case for specific syntax parameter in get_asm_parser() JanLJL 2025-03-04 17:45:19 +01:00
  • 253b0ee9d5 remove dependency on MachineModel JanLJL 2025-03-04 17:44:27 +01:00
  • b6c3c924c6 remove dependency on MachineModel JanLJL 2025-03-04 17:44:27 +01:00
  • e37f9f119d add default syntax for get_parser for compatibility with kerncraft JanLJL 2025-03-04 17:44:02 +01:00
  • 1be2f320b9 add default syntax for get_parser for compatibility with kerncraft JanLJL 2025-03-04 17:44:02 +01:00
  • 400be352e1 remove dependency on MachineModel JanLJL 2025-03-04 17:42:52 +01:00
  • 379e422290 remove dependency on MachineModel JanLJL 2025-03-04 17:42:52 +01:00
  • 62908f3b8f fix bug when no micro arch was given JanLJL 2025-03-04 17:42:05 +01:00
  • d772522400 fix bug when no micro arch was given JanLJL 2025-03-04 17:42:05 +01:00
  • 7e546d970f Parser for RISCV is implemented and tested with a simple kernel. Metehan Dundar 2025-03-04 00:44:38 +01:00
  • 34fef3823b get_marker() needed for kerncraft JanLJL 2025-03-03 18:26:33 +01:00
  • dbbbe743ac get_marker() needed for kerncraft JanLJL 2025-03-03 18:26:33 +01:00
  • 1a7c1588f6 Add support for the Intel syntax supported by MSVC and ICC pleroy 2025-02-02 14:02:16 +01:00
  • b4d342266d Add support for the Intel syntax supported by MSVC and ICC pleroy 2025-02-02 14:02:16 +01:00
  • 785a365c63 bugfix JanLJL 2025-01-09 17:11:21 +01:00
  • dffea6d066 bugfix JanLJL 2025-01-09 17:11:21 +01:00
  • 34321109df more SVE instructions JanLJL 2025-01-09 16:48:48 +01:00