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py/asmthumb: Extend load/store generators with ARMv7-M opcodes.
This commit lets the Thumb native code generator backend emit ARMv7-M
specific opcodes for indexed load/store operations if possible.
Now T3 opcode encodings are used if the generator backend is configured
to allow emitting ARMv7-M opcodes and if the (unsigned) scaled index
fits in 12 bits. Or, in other words, LDR{B,H}.W and STR{B,H}.W opcodes
are now emitted if possible.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit is contained in:
Alessandro Gatti
committed by
Damien George
Damien George
parent
78ee1bac60
commit
1f5ba6998b
@@ -40,6 +40,7 @@
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#define UNSIGNED_FIT5(x) ((uint32_t)(x) < 32)
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#define UNSIGNED_FIT7(x) ((uint32_t)(x) < 128)
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#define UNSIGNED_FIT8(x) (((x) & 0xffffff00) == 0)
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#define UNSIGNED_FIT12(x) (((x) & 0xfffff000) == 0)
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#define UNSIGNED_FIT16(x) (((x) & 0xffff0000) == 0)
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#define SIGNED_FIT8(x) (((x) & 0xffffff80) == 0) || (((x) & 0xffffff80) == 0xffffff80)
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#define SIGNED_FIT9(x) (((x) & 0xffffff00) == 0) || (((x) & 0xffffff00) == 0xffffff00)
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@@ -52,12 +53,6 @@
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#define OP_SUB_W_RRI_HI(reg_src) (0xf2a0 | (reg_src))
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#define OP_SUB_W_RRI_LO(reg_dest, imm11) ((imm11 << 4 & 0x7000) | reg_dest << 8 | (imm11 & 0xff))
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#define OP_LDR_W_HI(reg_base) (0xf8d0 | (reg_base))
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#define OP_LDR_W_LO(reg_dest, imm12) ((reg_dest) << 12 | (imm12))
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#define OP_LDRH_W_HI(reg_base) (0xf8b0 | (reg_base))
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#define OP_LDRH_W_LO(reg_dest, imm12) ((reg_dest) << 12 | (imm12))
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static inline byte *asm_thumb_get_cur_to_write_bytes(asm_thumb_t *as, int n) {
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return mp_asm_base_get_cur_to_write_bytes(&as->base, n);
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}
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@@ -432,11 +427,6 @@ void asm_thumb_mov_reg_pcrel(asm_thumb_t *as, uint rlo_dest, uint label) {
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asm_thumb_add_reg_reg(as, rlo_dest, ASM_THUMB_REG_R15); // 2 bytes
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}
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// ARMv7-M only
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static inline void asm_thumb_ldr_reg_reg_i12(asm_thumb_t *as, uint reg_dest, uint reg_base, uint word_offset) {
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asm_thumb_op32(as, OP_LDR_W_HI(reg_base), OP_LDR_W_LO(reg_dest, word_offset * 4));
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}
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// emits code for: reg_dest = reg_base + offset << offset_shift
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static void asm_thumb_add_reg_reg_offset(asm_thumb_t *as, uint reg_dest, uint reg_base, uint offset, uint offset_shift) {
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if (reg_dest < ASM_THUMB_REG_R8 && reg_base < ASM_THUMB_REG_R8) {
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@@ -464,30 +454,44 @@ static void asm_thumb_add_reg_reg_offset(asm_thumb_t *as, uint reg_dest, uint re
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}
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}
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void asm_thumb_ldr_reg_reg_i12_optimised(asm_thumb_t *as, uint reg_dest, uint reg_base, uint word_offset) {
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if (reg_dest < ASM_THUMB_REG_R8 && reg_base < ASM_THUMB_REG_R8 && UNSIGNED_FIT5(word_offset)) {
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asm_thumb_ldr_rlo_rlo_i5(as, reg_dest, reg_base, word_offset);
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} else if (asm_thumb_allow_armv7m(as)) {
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asm_thumb_ldr_reg_reg_i12(as, reg_dest, reg_base, word_offset);
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#define OP_LDR_STR_W_HI(shift, reg) ((0xf880 | (shift) << 5) | (reg))
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#define OP_LDR_STR_W_LO(reg, imm12) (((reg) << 12) | (imm12))
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#define OP_LDR 0x01
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#define OP_STR 0x00
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#define OP_LDR_W 0x10
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#define OP_STR_W 0x00
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static const uint8_t OP_LDR_STR_TABLE[3] = {
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0x0E, 0x10, 0x0C
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};
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void asm_thumb_load_reg_reg_offset(asm_thumb_t *as, uint reg_dest, uint reg_base, uint offset, uint shift) {
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if (UNSIGNED_FIT5(offset) && (reg_dest < ASM_THUMB_REG_R8) && (reg_base < ASM_THUMB_REG_R8)) {
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// Can use T1 encoding
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asm_thumb_op16(as, ((OP_LDR_STR_TABLE[shift] | OP_LDR) << 11) | (offset << 6) | (reg_base << 3) | reg_dest);
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} else if (asm_thumb_allow_armv7m(as) && UNSIGNED_FIT12(offset << shift)) {
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// Can use T3 encoding
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asm_thumb_op32(as, (OP_LDR_STR_W_HI(shift, reg_base) | OP_LDR_W), OP_LDR_STR_W_LO(reg_dest, (offset << shift)));
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} else {
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asm_thumb_add_reg_reg_offset(as, reg_dest, reg_base, word_offset - 31, 2);
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asm_thumb_ldr_rlo_rlo_i5(as, reg_dest, reg_dest, 31);
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// Must use the generic sequence
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asm_thumb_add_reg_reg_offset(as, reg_dest, reg_base, offset - 31, shift);
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asm_thumb_op16(as, ((OP_LDR_STR_TABLE[shift] | OP_LDR) << 11) | (31 << 6) | (reg_dest << 3) | (reg_dest));
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}
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}
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// ARMv7-M only
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static inline void asm_thumb_ldrh_reg_reg_i12(asm_thumb_t *as, uint reg_dest, uint reg_base, uint uint16_offset) {
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asm_thumb_op32(as, OP_LDRH_W_HI(reg_base), OP_LDRH_W_LO(reg_dest, uint16_offset * 2));
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}
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void asm_thumb_ldrh_reg_reg_i12_optimised(asm_thumb_t *as, uint reg_dest, uint reg_base, uint uint16_offset) {
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if (reg_dest < ASM_THUMB_REG_R8 && reg_base < ASM_THUMB_REG_R8 && UNSIGNED_FIT5(uint16_offset)) {
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asm_thumb_ldrh_rlo_rlo_i5(as, reg_dest, reg_base, uint16_offset);
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} else if (asm_thumb_allow_armv7m(as)) {
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asm_thumb_ldrh_reg_reg_i12(as, reg_dest, reg_base, uint16_offset);
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void asm_thumb_store_reg_reg_offset(asm_thumb_t *as, uint reg_src, uint reg_base, uint offset, uint shift) {
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if (UNSIGNED_FIT5(offset) && (reg_src < ASM_THUMB_REG_R8) && (reg_base < ASM_THUMB_REG_R8)) {
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// Can use T1 encoding
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asm_thumb_op16(as, ((OP_LDR_STR_TABLE[shift] | OP_STR) << 11) | (offset << 6) | (reg_base << 3) | reg_src);
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} else if (asm_thumb_allow_armv7m(as) && UNSIGNED_FIT12(offset << shift)) {
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// Can use T3 encoding
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asm_thumb_op32(as, (OP_LDR_STR_W_HI(shift, reg_base) | OP_STR_W), OP_LDR_STR_W_LO(reg_src, (offset << shift)));
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} else {
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asm_thumb_add_reg_reg_offset(as, reg_dest, reg_base, uint16_offset - 31, 1);
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asm_thumb_ldrh_rlo_rlo_i5(as, reg_dest, reg_dest, 31);
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// Must use the generic sequence
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asm_thumb_add_reg_reg_offset(as, reg_base, reg_base, offset - 31, shift);
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asm_thumb_op16(as, ((OP_LDR_STR_TABLE[shift] | OP_STR) << 11) | (31 << 6) | (reg_base << 3) | reg_src);
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}
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}
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@@ -569,7 +573,7 @@ void asm_thumb_b_rel12(asm_thumb_t *as, int rel) {
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void asm_thumb_bl_ind(asm_thumb_t *as, uint fun_id, uint reg_temp) {
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// Load ptr to function from table, indexed by fun_id, then call it
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asm_thumb_ldr_reg_reg_i12_optimised(as, reg_temp, ASM_THUMB_REG_FUN_TABLE, fun_id);
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asm_thumb_load_reg_reg_offset(as, reg_temp, ASM_THUMB_REG_FUN_TABLE, fun_id, 2);
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asm_thumb_op16(as, OP_BLX(reg_temp));
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}
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@@ -382,8 +382,10 @@ void asm_thumb_mov_reg_local(asm_thumb_t *as, uint rlo_dest, int local_num); //
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void asm_thumb_mov_reg_local_addr(asm_thumb_t *as, uint rlo_dest, int local_num); // convenience
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void asm_thumb_mov_reg_pcrel(asm_thumb_t *as, uint rlo_dest, uint label);
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void asm_thumb_ldr_reg_reg_i12_optimised(asm_thumb_t *as, uint reg_dest, uint reg_base, uint word_offset); // convenience
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void asm_thumb_ldrh_reg_reg_i12_optimised(asm_thumb_t *as, uint reg_dest, uint reg_base, uint uint16_offset); // convenience
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// Generate optimised load dest, [src, #offset] sequence
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void asm_thumb_load_reg_reg_offset(asm_thumb_t *as, uint reg_dest, uint reg_base, uint offset, uint shift);
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// Generate optimised store src, [dest, #offset] sequence
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void asm_thumb_store_reg_reg_offset(asm_thumb_t *as, uint reg_src, uint reg_base, uint offset, uint shift);
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void asm_thumb_b_label(asm_thumb_t *as, uint label); // convenience: picks narrow or wide branch
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void asm_thumb_bcc_label(asm_thumb_t *as, int cc, uint label); // convenience: picks narrow or wide branch
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@@ -463,17 +465,20 @@ void asm_thumb_b_rel12(asm_thumb_t *as, int rel);
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#define ASM_MUL_REG_REG(as, reg_dest, reg_src) asm_thumb_format_4((as), ASM_THUMB_FORMAT_4_MUL, (reg_dest), (reg_src))
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#define ASM_LOAD_REG_REG_OFFSET(as, reg_dest, reg_base, word_offset) ASM_LOAD32_REG_REG_OFFSET((as), (reg_dest), (reg_base), (word_offset))
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#define ASM_LOAD8_REG_REG(as, reg_dest, reg_base) asm_thumb_ldrb_rlo_rlo_i5((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD16_REG_REG(as, reg_dest, reg_base) asm_thumb_ldrh_rlo_rlo_i5((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD16_REG_REG_OFFSET(as, reg_dest, reg_base, uint16_offset) asm_thumb_ldrh_reg_reg_i12_optimised((as), (reg_dest), (reg_base), (uint16_offset))
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#define ASM_LOAD32_REG_REG(as, reg_dest, reg_base) asm_thumb_ldr_rlo_rlo_i5((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD32_REG_REG_OFFSET(as, reg_dest, reg_base, word_offset) asm_thumb_ldr_reg_reg_i12_optimised((as), (reg_dest), (reg_base), (word_offset))
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#define ASM_LOAD8_REG_REG(as, reg_dest, reg_base) ASM_LOAD8_REG_REG_OFFSET((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD8_REG_REG_OFFSET(as, reg_dest, reg_base, byte_offset) asm_thumb_load_reg_reg_offset((as), (reg_dest), (reg_base), (byte_offset), 0)
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#define ASM_LOAD16_REG_REG(as, reg_dest, reg_base) ASM_LOAD16_REG_REG_OFFSET((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD16_REG_REG_OFFSET(as, reg_dest, reg_base, halfword_offset) asm_thumb_load_reg_reg_offset((as), (reg_dest), (reg_base), (halfword_offset), 1)
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#define ASM_LOAD32_REG_REG(as, reg_dest, reg_base) ASM_LOAD32_REG_REG_OFFSET((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD32_REG_REG_OFFSET(as, reg_dest, reg_base, word_offset) asm_thumb_load_reg_reg_offset((as), (reg_dest), (reg_base), (word_offset), 2)
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#define ASM_STORE_REG_REG_OFFSET(as, reg_src, reg_base, word_offset) ASM_STORE32_REG_REG_OFFSET((as), (reg_src), (reg_base), (word_offset))
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#define ASM_STORE8_REG_REG(as, reg_src, reg_base) asm_thumb_strb_rlo_rlo_i5((as), (reg_src), (reg_base), 0)
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#define ASM_STORE16_REG_REG(as, reg_src, reg_base) asm_thumb_strh_rlo_rlo_i5((as), (reg_src), (reg_base), 0)
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#define ASM_STORE32_REG_REG(as, reg_src, reg_base) asm_thumb_str_rlo_rlo_i5((as), (reg_src), (reg_base), 0)
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#define ASM_STORE32_REG_REG_OFFSET(as, reg_src, reg_base, word_offset) asm_thumb_str_rlo_rlo_i5((as), (reg_src), (reg_base), (word_offset))
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#define ASM_STORE8_REG_REG(as, reg_src, reg_base) ASM_STORE8_REG_REG_OFFSET((as), (reg_src), (reg_base), 0)
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#define ASM_STORE8_REG_REG_OFFSET(as, reg_src, reg_base, byte_offset) asm_thumb_store_reg_reg_offset((as), (reg_src), (reg_base), (byte_offset), 0)
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#define ASM_STORE16_REG_REG(as, reg_src, reg_base) ASM_STORE16_REG_REG_OFFSET((as), (reg_src), (reg_base), 0)
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#define ASM_STORE16_REG_REG_OFFSET(as, reg_src, reg_base, halfword_offset) asm_thumb_store_reg_reg_offset((as), (reg_src), (reg_base), (halfword_offset), 1)
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#define ASM_STORE32_REG_REG(as, reg_src, reg_base) ASM_STORE32_REG_REG_OFFSET((as), (reg_src), (reg_base), 0)
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#define ASM_STORE32_REG_REG_OFFSET(as, reg_src, reg_base, word_offset) asm_thumb_store_reg_reg_offset((as), (reg_src), (reg_base), (word_offset), 2)
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#define ASM_LOAD8_REG_REG_REG(as, reg_dest, reg_base, reg_index) asm_thumb_ldrb_rlo_rlo_rlo((as), (reg_dest), (reg_base), (reg_index))
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#define ASM_LOAD16_REG_REG_REG(as, reg_dest, reg_base, reg_index) \
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@@ -1540,12 +1540,7 @@ static void emit_native_load_subscr(emit_t *emit) {
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#ifdef ASM_LOAD8_REG_REG_OFFSET
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ASM_LOAD8_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
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#else
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#if N_THUMB
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if (index_value >= 0 && index_value < 32) {
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asm_thumb_ldrb_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value);
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break;
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}
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#elif N_RV32
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#if N_RV32
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if (FIT_SIGNED(index_value, 12)) {
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asm_rv32_opcode_lbu(emit->as, REG_RET, reg_base, index_value);
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break;
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@@ -1572,12 +1567,7 @@ static void emit_native_load_subscr(emit_t *emit) {
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#ifdef ASM_LOAD16_REG_REG_OFFSET
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ASM_LOAD16_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
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#else
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#if N_THUMB
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if (index_value >= 0 && index_value < 32) {
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asm_thumb_ldrh_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value);
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break;
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}
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#elif N_RV32
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#if N_RV32
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if (FIT_SIGNED(index_value, 11)) {
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asm_rv32_opcode_lhu(emit->as, REG_RET, reg_base, index_value << 1);
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break;
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@@ -1604,12 +1594,7 @@ static void emit_native_load_subscr(emit_t *emit) {
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#ifdef ASM_LOAD32_REG_REG_OFFSET
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ASM_LOAD32_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
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#else
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#if N_THUMB
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if (index_value >= 0 && index_value < 32) {
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asm_thumb_ldr_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value);
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break;
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}
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#elif N_RV32
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#if N_RV32
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if (FIT_SIGNED(index_value, 10)) {
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asm_rv32_opcode_lw(emit->as, REG_RET, reg_base, index_value << 2);
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break;
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@@ -1824,13 +1809,7 @@ static void emit_native_store_subscr(emit_t *emit) {
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#ifdef ASM_STORE8_REG_REG_OFFSET
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ASM_STORE8_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
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#else
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// TODO optimise to use thumb strb r1, [r2, r3]
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#if N_THUMB
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if (index_value >= 0 && index_value < 32) {
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asm_thumb_strb_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value);
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break;
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}
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#elif N_RV32
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#if N_RV32
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if (FIT_SIGNED(index_value, 12)) {
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asm_rv32_opcode_sb(emit->as, reg_value, reg_base, index_value);
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break;
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@@ -1860,12 +1839,7 @@ static void emit_native_store_subscr(emit_t *emit) {
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#ifdef ASM_STORE16_REG_REG_OFFSET
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ASM_STORE16_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
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#else
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#if N_THUMB
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if (index_value >= 0 && index_value < 32) {
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asm_thumb_strh_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value);
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break;
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}
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#elif N_RV32
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#if N_RV32
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if (FIT_SIGNED(index_value, 11)) {
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asm_rv32_opcode_sh(emit->as, reg_value, reg_base, index_value << 1);
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break;
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@@ -1891,12 +1865,7 @@ static void emit_native_store_subscr(emit_t *emit) {
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#ifdef ASM_STORE32_REG_REG_OFFSET
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ASM_STORE32_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
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#else
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#if N_THUMB
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if (index_value >= 0 && index_value < 32) {
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asm_thumb_str_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value);
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break;
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}
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#elif N_RV32
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#if N_RV32
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if (FIT_SIGNED(index_value, 10)) {
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asm_rv32_opcode_sw(emit->as, reg_value, reg_base, index_value << 2);
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break;
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