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stm32/boards/NUCLEO_N657X0: Add new board definition files.

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Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George
2024-06-18 17:46:54 +10:00
parent 3189e49d28
commit 50ea398b00
8 changed files with 395 additions and 0 deletions
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42
ports/stm32/boards/NUCLEO_N657X0/bdev.c Normal file
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2025 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/obj.h"
#include "storage.h"
#include "xspi.h"
#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
#error "Cannot enable MICROPY_HW_SPIFLASH_ENABLE_CACHE"
#endif
// External SPI flash uses hardware XSPI interface.
const mp_spiflash_config_t spiflash_config = {
.bus_kind = MP_SPIFLASH_BUS_QSPI,
.bus.u_qspi.data = (void *)&xspi_flash2,
.bus.u_qspi.proto = &xspi_proto,
};
spi_bdev_t spi_bdev;

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ports/stm32/boards/NUCLEO_N657X0/board.c Normal file
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2024-2025 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/mphal.h"
#include "boardctrl.h"
#include "xspi.h"
// Values for OTP fuses for VDDIO3, to select low voltage mode (<2.5V).
// See RM0486, Section 5, Table 18.
#define BSEC_HW_CONFIG_ID (124U)
#define BSEC_HWS_HSLV_VDDIO3 (1U << 15)
static void board_config_vdd(void) {
// TODO: move some of the below code to a common location for all N6 boards?
// Enable PWR, BSEC and SYSCFG clocks.
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
// Program high speed IO optimization fuses if they aren't already set.
uint32_t fuse;
BSEC_HandleTypeDef hbsec = { .Instance = BSEC };
const uint32_t mask = BSEC_HWS_HSLV_VDDIO3;
if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
fuse = 0;
} else if ((fuse & mask) != mask) {
// Program the fuse, and read back the set value.
if (HAL_BSEC_OTP_Program(&hbsec, BSEC_HW_CONFIG_ID, fuse | mask, HAL_BSEC_NORMAL_PROG) != HAL_OK) {
fuse = 0;
} else if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
fuse = 0;
}
}
// Enable Vdd ADC, needed for the ADC to work.
LL_PWR_EnableVddADC();
// Configure VDDIO2.
LL_PWR_EnableVddIO2();
LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
// Configure VDDIO3. Only enable 1.8V mode if the fuse is set.
LL_PWR_EnableVddIO3();
if (fuse & BSEC_HWS_HSLV_VDDIO3) {
LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
}
SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
// Configure VDDIO4.
LL_PWR_EnableVddIO4();
LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
// Enable VDD for ADC and USB.
LL_PWR_EnableVddADC();
LL_PWR_EnableVddUSB();
}
void mboot_board_early_init(void) {
board_config_vdd();
xspi_init();
}
void board_early_init(void) {
#if !MICROPY_HW_RUNS_FROM_EXT_FLASH
// Firmware runs directly from SRAM, so configure VDD and enable XSPI flash.
board_config_vdd();
xspi_init();
#endif
}
void board_leave_standby(void) {
// TODO: move some of the below code to a common location for all N6 boards?
// Enable PWR, BSEC and SYSCFG clocks.
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
// Configure VDDIO2.
LL_PWR_EnableVddIO2();
LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
// Configure VDDIO3 (1.8V mode selection is retained).
LL_PWR_EnableVddIO3();
SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
// Configure VDDIO4.
LL_PWR_EnableVddIO4();
LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
// Enable VDD for ADC and USB.
LL_PWR_EnableVddADC();
LL_PWR_EnableVddUSB();
}

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ports/stm32/boards/NUCLEO_N657X0/board.md Normal file
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The mboot bootloader must first be built and deployed to this board. Make sure that
CN9 is in position 1-2 to select STLK as the 5V power source, that JP1 is in position
1-2 (lower position) and JP2 is in position 2-3 (upper position). Then plug in a USB
cable into the ST-LINK port CN10. This will allow mboot firmware to be programmed to
the external SPI flash via ST's tools, eg:
make -C ports/stm32/mboot BOARD=NUCLEO_N657X0 deploy-trusted
Once mboot is installed, change CN9 to position 3-4 to select USB as the 5V power
source, change JP2 back to position 1-2 (lower position) and change the USB cable to
CN8. mboot will present a USB DFU device on this USB port, and the red LED2 should be
blinking at 1Hz to indicate that mboot is active. If it's not active then hold the
USER button and press NRST, and wait until all three LEDs are on, then release USER.
Now mboot will be active.
Once the USB DFU port can be seen, the firmware below can be programmed as usual with
any DFU loader.

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ports/stm32/boards/NUCLEO_N657X0/mpconfigboard.h Normal file
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#define MICROPY_HW_BOARD_NAME "NUCLEO-N657X0"
#define MICROPY_HW_MCU_NAME "STM32N657X0"
#define MICROPY_GC_STACK_ENTRY_TYPE uint32_t
#define MICROPY_ALLOC_GC_STACK_SIZE (128)
#define MICROPY_FATFS_EXFAT (1)
#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
#define MICROPY_HW_HAS_SWITCH (1)
#define MICROPY_HW_HAS_FLASH (1)
#define MICROPY_HW_ENABLE_RNG (1)
#define MICROPY_HW_ENABLE_RTC (1)
#define MICROPY_HW_ENABLE_DAC (0)
#define MICROPY_HW_ENABLE_USB (1)
#define MICROPY_PY_PYB_LEGACY (0)
#define MICROPY_BOARD_EARLY_INIT board_early_init
#define MICROPY_BOARD_LEAVE_STANDBY board_leave_standby()
// HSE is 48MHz, this gives a CPU frequency of 800MHz.
#define MICROPY_HW_CLK_PLLM (6)
#define MICROPY_HW_CLK_PLLN (100)
#define MICROPY_HW_CLK_PLLP1 (1)
#define MICROPY_HW_CLK_PLLP2 (1)
#define MICROPY_HW_CLK_PLLFRAC (0)
// The LSE is a 32kHz crystal.
#define MICROPY_HW_RTC_USE_LSE (1)
#define MICROPY_HW_RTC_USE_US (1)
// External SPI flash, MX25UM51245GXDI00.
#define MICROPY_HW_XSPIFLASH_SIZE_BITS_LOG2 (29)
// SPI flash, block device config.
#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev)
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev)
#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config)
#define MICROPY_HW_BDEV_SPIFLASH_OFFSET_BYTES (4 * 1024 * 1024)
#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (60 * 1024 * 1024)
// UART buses
#define MICROPY_HW_UART1_TX (pyb_pin_UART1_TX)
#define MICROPY_HW_UART1_RX (pyb_pin_UART1_RX)
#define MICROPY_HW_UART3_TX (pyb_pin_UART3_TX)
#define MICROPY_HW_UART3_RX (pyb_pin_UART3_RX)
#define MICROPY_HW_UART_REPL (PYB_UART_1)
#define MICROPY_HW_UART_REPL_BAUD (115200)
// I2C buses
#define MICROPY_HW_I2C1_SCL (pyb_pin_I2C1_SCL)
#define MICROPY_HW_I2C1_SDA (pyb_pin_I2C1_SDA)
// SPI buses
#define MICROPY_HW_SPI5_NSS (pyb_pin_SPI5_CS)
#define MICROPY_HW_SPI5_SCK (pyb_pin_SPI5_SCK)
#define MICROPY_HW_SPI5_MISO (pyb_pin_SPI5_MISO)
#define MICROPY_HW_SPI5_MOSI (pyb_pin_SPI5_MOSI)
// USER2 is floating, and pressing the button makes the input go high.
#define MICROPY_HW_USRSW_PIN (pyb_pin_BUTTON)
#define MICROPY_HW_USRSW_PULL (GPIO_PULLDOWN)
#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING)
#define MICROPY_HW_USRSW_PRESSED (1)
// LEDs
#define MICROPY_HW_LED1 (pyb_pin_LED_RED)
#define MICROPY_HW_LED2 (pyb_pin_LED_GREEN)
#define MICROPY_HW_LED3 (pyb_pin_LED_BLUE)
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
// USB config
#define MICROPY_HW_USB_HS (1)
#define MICROPY_HW_USB_HS_IN_FS (1)
#define MICROPY_HW_USB_MAIN_DEV (USB_PHY_HS_ID)
/******************************************************************************/
// Bootloader configuration
#define MBOOT_BOARD_EARLY_INIT(initial_r0) mboot_board_early_init()
#define MBOOT_SPIFLASH_CS (pyb_pin_XSPIM_P2_CS)
#define MBOOT_SPIFLASH_SCK (pyb_pin_XSPIM_P2_SCK)
#define MBOOT_SPIFLASH_MOSI (pyb_pin_XSPIM_P2_IO0)
#define MBOOT_SPIFLASH_MISO (pyb_pin_XSPIM_P2_IO1)
#define MBOOT_SPIFLASH_ADDR (0x70000000)
#define MBOOT_SPIFLASH_BYTE_SIZE (64 * 1024 * 1024)
#define MBOOT_SPIFLASH_LAYOUT "/0x70000000/16384*4Kg"
#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1)
#define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash)
#define MBOOT_SPIFLASH_CONFIG (&spiflash_config)
/******************************************************************************/
// Function and variable declarations
extern const struct _mp_spiflash_config_t spiflash_config;
extern struct _spi_bdev_t spi_bdev;
void mboot_board_early_init(void);
void mboot_board_entry_init(void);
void board_early_init(void);
void board_leave_standby(void);

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ports/stm32/boards/NUCLEO_N657X0/mpconfigboard.mk Normal file
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# Without mboot, the main firmware must fit in 512k flash, will be copied to SRAM by
# the hardware bootloader, and will run from SRAM. With mboot, the main firmware can
# be much larger and will run from flash via XSPI in memory-mapped mode.
USE_MBOOT ?= 1
MCU_SERIES = n6
CMSIS_MCU = STM32N657xx
AF_FILE = boards/stm32n657_af.csv
ifeq ($(BUILDING_MBOOT),1)
SYSTEM_FILE = $(STM32LIB_CMSIS_BASE)/Source/Templates/system_stm32$(MCU_SERIES)xx_fsbl.o
else
SYSTEM_FILE = $(STM32LIB_CMSIS_BASE)/Source/Templates/system_stm32$(MCU_SERIES)xx_s.o
endif
STM32_N6_HEADER_VERSION = 2.1
DKEL = $(STM32_CUBE_PROGRAMMER)/bin/ExternalLoader/MX25UM51245G_STM32N6570-NUCLEO.stldr
ifeq ($(USE_MBOOT),1)
LD_FILES = boards/stm32n657x0.ld boards/common_n6_flash.ld
TEXT0_ADDR = 0x70080000
else
LD_FILES = boards/stm32n657x0.ld boards/common_basic.ld
TEXT0_ADDR = 0x34180400
endif
# MicroPython settings
MICROPY_FLOAT_IMPL = double

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ports/stm32/boards/NUCLEO_N657X0/partition_stm32n657xx.h Normal file
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// This board does not use any security settings, so can just stay in secure
// mode without configuring the SAU.
static inline void TZ_SAU_Setup(void) {
}

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ports/stm32/boards/NUCLEO_N657X0/pins.csv Normal file
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D0,PD9
D1,PD8
D2,PD0
D3,PE9
D4,PE0
D5,PE10
D6,PD5
D7,PE11
D8,PD12
D9,PD7
D10,PA3
D11,PG2
D12,PG1
D13,PE15
D14,PC1
D15,PH9
# Ax header pins are connected directly to the following digital IO
A0D,PF5
A1D,PC10
A2D,PF6
A3D,PA2
A4D,PC12
A5D,PH2
# Ax header pins are connected to the following analog IO via an op-amp in voltage-follower mode running at 1.8V
A0,PA8
A1,PA9
A2,PA10
A3,PA12
A4,PF3
A5,PG15
-UART1_TX,PE5
-UART1_RX,PE6
-UART3_TX,PD8
-UART3_RX,PD9
-I2C1_SCL,PH9
-I2C1_SDA,PC1
-SPI5_CS,PA3
-SPI5_SCK,PE15
-SPI5_MISO,PG1
-SPI5_MOSI,PG2
-BUTTON,PC13
LED_BLUE,PG8
LED_RED,PG10
LED_GREEN,PG0
-XSPIM_P2_DQS,PN0
-XSPIM_P2_CS,PN1
-XSPIM_P2_IO0,PN2
-XSPIM_P2_IO1,PN3
-XSPIM_P2_IO2,PN4
-XSPIM_P2_IO3,PN5
-XSPIM_P2_SCK,PN6
-XSPIM_P2_IO4,PN8
-XSPIM_P2_IO5,PN9
-XSPIM_P2_IO6,PN10
-XSPIM_P2_IO7,PN11
Can't render this file because it has a wrong number of fields in line 18.

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ports/stm32/boards/NUCLEO_N657X0/stm32n6xx_hal_conf.h Normal file
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/* This file is part of the MicroPython project, http://micropython.org/
* The MIT License (MIT)
* Copyright (c) 2019 Damien P. George
*/
#ifndef MICROPY_INCLUDED_STM32N6XX_HAL_CONF_H
#define MICROPY_INCLUDED_STM32N6XX_HAL_CONF_H
// Oscillator values in Hz
#define HSE_VALUE (48000000)
#define LSE_VALUE (32768)
// Oscillator timeouts in ms
#define HSE_STARTUP_TIMEOUT (100)
#define LSE_STARTUP_TIMEOUT (5000)
#include "boards/stm32n6xx_hal_conf_base.h"
#endif // MICROPY_INCLUDED_STM32N6XX_HAL_CONF_H