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py/emitnative: Remove redundant RV32 Viper int-indexed code.

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This commit removes redundant RV32 implementations of certain
int-indexed code generation operations (32-bit load/store and 16-bit
load).

Those operations were already available as part of the native emitter
API but were not exposed to the Viper code generator.  As part of the
introduction of more specialised load and store API calls to
int-indexed Viper load/store generator bits, the existing native emitter
implementations are reused, thus making the Viper implementations
redundant.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit is contained in:
Alessandro Gatti
2025-05-22 14:03:53 +02:00
committed by Damien George
parent 84ad2c6cd0
commit 901c96dc55
1 changed files with 0 additions and 18 deletions
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18
py/emitnative.c
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@@ -1567,12 +1567,6 @@ static void emit_native_load_subscr(emit_t *emit) {
#ifdef ASM_LOAD16_REG_REG_OFFSET
ASM_LOAD16_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
#else
#if N_RV32
if (FIT_SIGNED(index_value, 11)) {
asm_rv32_opcode_lhu(emit->as, REG_RET, reg_base, index_value << 1);
break;
}
#endif
if (index_value != 0) {
// index is a non-zero immediate
need_reg_single(emit, reg_index, 0);
@@ -1589,12 +1583,6 @@ static void emit_native_load_subscr(emit_t *emit) {
#ifdef ASM_LOAD32_REG_REG_OFFSET
ASM_LOAD32_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
#else
#if N_RV32
if (FIT_SIGNED(index_value, 10)) {
asm_rv32_opcode_lw(emit->as, REG_RET, reg_base, index_value << 2);
break;
}
#endif
if (index_value != 0) {
// index is a non-zero immediate
need_reg_single(emit, reg_index, 0);
@@ -1855,12 +1843,6 @@ static void emit_native_store_subscr(emit_t *emit) {
#ifdef ASM_STORE32_REG_REG_OFFSET
ASM_STORE32_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
#else
#if N_RV32
if (FIT_SIGNED(index_value, 10)) {
asm_rv32_opcode_sw(emit->as, reg_value, reg_base, index_value << 2);
break;
}
#endif
if (index_value != 0) {
// index is a non-zero immediate
#if N_ARM