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tests/extmod_hardware/machine_uart_irq_rxidle.py: Ignore inital IRQ.

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On stm32, the hardware generates an RXIDLE IRQ after enabling the UART,
because the RX line is technically idle.

Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George
2025-06-26 00:29:22 +10:00
parent a2e3055d2d
commit a4a098ff82
1 changed files with 11 additions and 0 deletions
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11
tests/extmod_hardware/machine_uart_irq_rxidle.py
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@@ -13,6 +13,9 @@ except (ImportError, AttributeError):
import time, sys
# Target tuning options.
tune_wait_initial_rxidle = False
# Configure pins based on the target.
if "alif" in sys.platform:
uart_id = 1
@@ -26,6 +29,7 @@ elif "mimxrt" in sys.platform:
uart_id = 1
tx_pin = None
elif "pyboard" in sys.platform:
tune_wait_initial_rxidle = True
if "STM32WB" in sys.implementation._machine:
# LPUART(1) is on PA2/PA3
uart_id = "LP1"
@@ -69,8 +73,15 @@ for bits_per_s in (2400, 9600, 115200):
else:
uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
# Ignore a possible initial RXIDLE condition after creating UART.
if tune_wait_initial_rxidle:
uart.irq(lambda _: None, uart.IRQ_RXIDLE)
time.sleep_ms(10)
# Configure desired IRQ.
uart.irq(irq, uart.IRQ_RXIDLE)
# Write data and wait for IRQ.
print("write", bits_per_s)
uart.write(text)
uart.flush()