The buffer was be reset on every call to uart.init(). If no sizes were
given, the buffer was set to the default size 256. That made problems
e.g. with PPP.
This commit fixes it, keeping the buffer size if not deliberately changed
and allocating new buffers only if the size was changed. Cater for changes
of the bits value, which requires a change to the buffer size.
Signed-off-by: robert-hh <robert@hammelrath.com>
The buffer was be reset on every call to uart.init(). If no sizes were
given, the buffer was set to the default size 256. That made problems e.g.
with PPP.
This commit fixes it, keeping the buffer size if not deliberately changed
and allocating new buffers only if the size was changed.
Signed-off-by: robert-hh <robert@hammelrath.com>
Changes:
- Move setting of PendSV priority to pendsv_init().
- Call pendsv_init() from CPU1 as well, to ensure priority is the same.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
A better indication of whether a cyw43 event is pending is the actual flag
in the PendSV handler table. (If this fails, could also use the GPIO
interrupt enabled register bit).
This commit was needed of a previous version of the fix in the parent
commit, but it turned out not strictly necessary for the current version.
However, it's still a good clean up.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
There's a very odd but predictable sequence of events that breaks Wi-Fi
when using both cores:
1) CPU1 calls pendsv_suspend() - for example sleep() causes
a softtimer node to be inserted, which calls pendsv_suspend().
2) CYW43 sends wakeup IRQ. CPU0 GPIO IRQ handler schedules PendSV
and disables the GPIO IRQ on CPU0, to re-enable after
cyw43_poll() runs and completes.
3) CPU0 PendSV_Handler runs, sees pendsv is suspended, exits.
4) CPU1 calls pendsv_resume() and pendsv_resume() sees PendSV
is pending and triggers it on CPU1.
5) CPU1 runs PendSV_Handler, runs cyw43_poll(), and at the end
it re-enables the IRQ *but now on CPU1*.
However CPU1 has GPIO IRQs disabled, so the CYW43 interrupt never runs
again...
The fix in this commit is to always enable/disable the interrupt on CPU0.
This isn't supported by the pico-sdk, but it is supported by the hardware.
Fixes issue #16779.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
It's common with write-only SPI displays for MISO to be repurposed as a
register select or data/command pin.
While that was possible by setting up the pin after a call to
`machine.SPI()` this change makes `machine.SPI(miso=None)` explicit.
Signed-off-by: Phil Howard <github@gadgetoid.com>
If the "spi_id" arg is not supplied and then the board default specified by
PICO_DEFAULT_SPI will be used.
Signed-off-by: Phil Howard <github@gadgetoid.com>
When PICO_DEFAULT_I2C is not set require an I2C bus ID instead of
using -1 as a default, which would fail with a cryptic:
"I2C(-1) doesn't exist"
Signed-off-by: Phil Howard <github@gadgetoid.com>
Some rp2 boards include WiFi, at least with the very popular Pico W and
Pico 2 W. New users frequently ask how to set up WiFi and are confused
because it's not covered in the quickref.
This commit adds the wlan section, copied and modified with notes from the
ESP32 quickref.
Signed-off-by: Matt Trentini <matt.trentini@gmail.com>
The IOTNODE_LORAWAN_RP2350 has an SD card and we want users to be able to
`import sdcard` without copying `sdcard.py` over to their board.
Signed-off-by: Malcolm McKellips <malcolm.mckellips@sparkfun.com>
stm32's QSPI driver supports memory-mapped mode. The memory-mapped flash
can also be erased/written to. To support both these modes, it switches in
and out of memory-mapped mode during an erase/write.
If the flash is erased/written and then switched back to memory mapped
mode, the cache related to the memory-mapped region that changed must be
invalidated. Otherwise subsequent code may end up reading old data.
That cache invalidation is currently not being done, and this commit fixes
that.
This bug has been around ever since QSPI memory-mapped mode existed, but
it's never really been observed because it's not common to use flash in
memory-mapped mode and also erase/write it. Eg PYBD_SF2 uses the
memory-mapped flash in read-only mode to store additional firmware.
But since the introduction of ROMFS, things changed. The `vfs.rom_ioctl()`
command can erase/write memory-mapped flash.
Signed-off-by: Damien George <damien@micropython.org>
Since all boards are configured to have a I2C(0), SPI(0) and UART(1), these
can be set as default devices, allowing the instantiation of I2C(), SPI(),
UART() without an id argument.
Signed-off-by: robert-hh <robert@hammelrath.com>
Set the default timeout to 50000 us. The default used to be 0, causing the
NXP I2C driver to silently stop working in case of a non-responding device.
Signed-off-by: robert-hh <robert@hammelrath.com>
The buffer would be reset on every call to `uart.init()`. If no sizes were
given, the buffer would be set to the default size 256. That made problems
e.g. with PPP. Also, the RX buffer was not stored at the UART object and
not visible to GC as being in use. Then a `gc.collect()` would eventually
free the buffer.
This commit fixes those issues, keeping the buffer size if not deliberately
changed and allocating new buffers only if the size was changed.
Signed-off-by: robert-hh <robert@hammelrath.com>
The flash devices used by the MIMXRT board are specified either with 3ns or
5 ns CS setup and hold time. Since a single configuration file is used for
all boards, use 5ns instead of 3ns to be safe, even if there were no
problems so far.
Signed-off-by: robert-hh <robert@hammelrath.com>
Changes:
- The duplicate LPUART_Init call was not needed, just an edit fail.
- Allow a port to disable UART.irq(). Some code for configuration stays,
but the respective UART IRQ is not enabled. Calling uart.irq() will
cause an exception by extmod/machine_uart.c.
Signed-off-by: robert-hh <robert@hammelrath.com>
PPP is now enabled on all boards with Ethernet support. PPP could be
enabled for other boards without Ethernet like the Teensy 4.0 as well in a
second step. Enabling for MIMXRT101x boards is hardly possible due to the
large RAM demand of lwIP.
Tested with a Teensy 4.1 board and a SimCom A7608 GPRS/LTE modem.
Signed-off-by: robert-hh <robert@hammelrath.com>
There is plenty of room in the MIMXRT board flash, so it can be enabled.
Tested with:
- MIMXRT1176_EVK
- MIMXRT1061 (Teensy 4.1)
- MIMXRT1010 (Olimex RT1010)
Signed-off-by: robert-hh <robert@hammelrath.com>
This is a board based on the i.MX RT1011 in breadboard-friendly shape. A
good basic board with 16M flash and regular pinout, providing access to
many GPIO_nn and GPIO_AD_nn Pins.
Signed-off-by: robert-hh <robert@hammelrath.com>
This commit removes the assumption made by the CI scripts that the
system-provided python executable is simply named "python". The scripts
will now look for a binary called "python3" first, and then fall back to
"python" if that is not found.
Whilst this is currently the case for the CI environment, there are no
guarantees for this going forward. For example minimal CI environments
set up by some developers, using the same base OS, have their python
executable called "python3".
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit expands the CI tests by checking whether the example native
modules are able to be built for the Xtensa architecture.
This was made possible by the changes to mpy_ld that allow symbol
resolution across standard compiler-provided libraries.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit introduces an additional symbol resolution mechanism to the
natmod linking process. This allows the build scripts to look for required
symbols into selected libraries that are provided by the compiler
installation (libgcc and libm at the moment).
For example, using soft-float code in natmods, whilst technically possible,
was not an easy process and required some additional work to pull it off.
With this addition all the manual (and error-prone) operations have been
automated and folded into `tools/mpy_ld.py`.
Both newlib and picolibc toolchains are supported, albeit the latter may
require a bit of extra configuration depending on the environment the build
process runs on. Picolibc's soft-float functions aren't in libm - in fact
the shipped libm is nothing but a stub - but they are inside libc. This is
usually not a problem as these changes cater for that configuration quirk,
but on certain compilers the include paths used to find libraries in may
not be updated to take Picolibc's library directory into account. The bare
metal RISC-V compiler shipped with the CI OS image (GCC 10.2.0 on Ubuntu
22.04LTS) happens to exhibit this very problem.
To work around that for CI builds, the Picolibc libraries' path is
hardcoded in the Makefile directives used by the linker, but this can be
changed by setting the PICOLIBC_ROOT environment library when building
natmods.
Signed-off-by: Volodymyr Shymanskyy <vshymanskyi@gmail.com>
Co-authored-by: Alessandro Gatti <a.gatti@frob.it>
Currently only classic CAN, but tests run on both the stm32 classic CAN
controller and the FD-CAN controller with the same results.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
This is necessary for the machine.CAN implementation to use the same
low-level functions.
Includes some refactoring around FIFO selection as there was a footgun
where CAN_FIFO0/1 are 0/1 but FDCAN_RX_FIFO0/1 are not. Added an explicit
type for non-hardware-specific FIFO numbering.
Also moved responsibility for re-enabling CAN receive interrupts into the
higher layer (pyb_can.c layer) after calling can_receive().
Also includes this behaviour change for FDCAN boards:
- Fix for boards with FDCAN not updating error status
counters (num_error_warning, num_error_passive, num_bus_off). These are
now updated the same as on boards with CAN Classic controllers, as
documented.
- Previously FDCAN boards would trigger the RX callback function on error
events instead (passing undocumented irq numbers 3, 4, 5).
This behaviour has been removed in favour of the documented behaviour of
updating the status counters.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Change ROMFS partition configuration variables to use index 0 as the
starting partition number (instead of index 1).
Reasons to do this:
- `vfs.rom_ioctl()` numbers the partitions starting from 0
- `mpremote romfs -p <partition id>` numbers the partitions starting from 0
Signed-off-by: Damien George <damien@micropython.org>
Similar to parent commit, allow using USB Serial/JTAG pins for other
purposes but only if this feature is disabled in the build config.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
When we don't use USB JTAG, we want to use the two USB pins (D+/D-) as
GPIO. So, do clear USB_SERIAL_JTAG_USB_PAD_ENABLE when USB SERIAL JTAG is
not enabled
Signed-off-by: Garry W <32130780+garywill@users.noreply.github.com>
Signed-off-by: Angus Gratton <angus@redyak.com.au>
The ESP32 PWM (LEDC) timer wasn't correctly stopped. `ledc_timer_rst()` is
for resetting the timer counter to zero, not for stopping the timer.
The correct way to stop a pwm timer is to pause it, then configure it with
`deconfigure = true`.
Signed-off-by: garywill <garywill@disroot.org>
This increases binary size by about 4KB on C3, probably a bit less on S2.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
These micros don't have full SDMMC host support, but they can initialise
the SDCard in SPI mode.
A bit limited on C3 and C6 as they only have one host SPI peripheral.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Previously ESP32-S3 SDMMC could only use fixed pin assignments, however the
ESP-IDF defaults don't match common boards. The chip also supports using
GPIO Matrix to assign any pin.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Reverts workaround added in acbdbcd9.
According to the linked ESP-IDF issue this was only a problem for ESP-IDF
V5.0.x, and support for versions older than V5.2 was dropped in 6e5d8d009.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Removes redundant metadata from each, shouldn't otherwise change
any build output.
Reverts the split originally added in e4650125.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
