The right service call to get UID is SERVICES_system_get_eui_extension
which returns an 8 bytes UID.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The byte order (endianness) seems to be swapped when read in 8D-8D-8D in
XIP mode, for most flashes, with the exception of MX which seems to swap
half-words.
This commit adds a flash setting to allow parts to enable half-word swap
when data is written, to fix this issue. By default, only endianness is
fixed.
Tested with both MX and ISSI parts on AE3, flash test and simple file
write/read.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The OSPI controller supports concurrent direct/XIP accesses, there's no
need to disable XIP on direct access. In addition to improving the
performance, this change lays the groundwork for supporting access by
the HP and HE cores simultaneously.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This change increases XIP read speed to ~30Mbytes/s at 50MHz DDR:
- Enable continuous mode.
- Remove hard-coded settings.
- Set XIP continuous mode timeout.
The prefetch remains disabled. Although enabling the prefetch gives the
best performance for the CPU in XIP mode, it must be disabled when the NPU
accesses the OSPI flash.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Leaving this pin low in combination with the default EM settings enables
flash protection for the EM flash.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The default dummy cycles may not match the actual flash frequency supported
by a certain board. For example, the MX chip uses 20 dummy cycles by
default which supports up to 200MHz DDR, but the maximum frequency
supported by the AE3 board is 50MHz DDR. So the dummy cycles for this
board can be as low as 6. It's important to set the correct dummy cycles,
as it results in doubling the XIP read speed, in the case of the AE3 board.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit enables detecting the flash device in runtime, and uses the
settings of the detected device instead of board-defined flash settings.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The same MicroPython firmware is built for the HE but with slightly
different options, for example no USB.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
With this new Makefile you can build the following:
make BOARD=MY_BOARD MCU_CORE=M55_HP # build HP firmware/ToC.
make BOARD=MY_BOARD MCU_CORE=M55_HE # build HE firmware/ToC.
make BOARD=MY_BOARD MCU_CORE=M55_DUAL # build HE+HP firmware + ToC.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Includes services to get random numbers, reset SoC, get unique-id, dump SoC
info, and CPU control services.
Signed-off-by: Damien George <damien@micropython.org>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit adds the beginning of a new alif port with support for Alif
Ensemble MCUs. See https://alifsemi.com/
Supported features of this port added by this commit:
- UART REPL.
- TinyUSB support, for REPL and MSC.
- Octal SPI flash support, for filesystem.
- machine.Pin support.
General notes about the port:
- It uses make, similar to other bare-metal ports here.
- The toolchain is the standard arm-none-eabi- toolchain.
- Flashing a board can be done using either the built-in serial bootloader,
or JLink (both supported here).
- There are two required submodules (one for drivers/SDK, one for security
tools), both of which are open source and on GitHub.
- No special hardware or software is needed for development, just a board
connected over USB.
OpenMV have generously sponsored the development of this port.
Signed-off-by: Damien George <damien@micropython.org>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The cyw43-driver now provides the Bluetooth initialisation code, making
`drivers/cyw43/cywbt.c` obsolete. To use the new code a port must enable
the `CYW43_ENABLE_BLUETOOTH_OVER_UART` option.
Some ports have yet to migrate to the new code, so in the meantime they can
explicitly add the old source to their source list and continue to use it
without change.
Signed-off-by: Damien George <damien@micropython.org>
Configure flash timings dynamically to match the system clock. Reconfigure
timings after flash writes.
Changes are:
- ports/rp2/main.c: Set default flash timings.
- ports/rp2/modmachine.c: Configure optimal flash timings on freq change.
- ports/rp2/rp2_flash.c: Reconfigure flash when leaving critical section.
Signed-off-by: Phil Howard <github@gadgetoid.com>
Add a 256 byte (FLASH_PAGE_SIZE) SRAM copy buffer to allow copies from
PSRAM to flash. This would otherwise hardfault since PSRAM is disabled
when doing a write to flash.
Changes are:
- ports/rp2/rp2_flash.c: Add 256 byte (flash page size) SRAM copy buffer
for PSRAM to flash copies.
- ports/rp2/rp2_flash.c: Invalidate the XIP cache to purge any PSRAM
data before critical flash operations.
Co-authored-by: Phil Howard <github@gadgetoid.com>
Co-authored-by: Angus Gratton <angus@redyak.com.au>
Signed-off-by: Phil Howard <github@gadgetoid.com>
PSRAM will be used exclusively if MICROPY_GC_SPLIT_HEAP == 0, it will be
added to RAM if MICROPY_GC_SPLIT_HEAP == 1, and the system will fall back
to RAM only if it's not detected.
Due to the size of PSRAM, GC stack was overflowing and causing the GC to
scan through the entire memory pool. This caused noticable slowdowns
during GC. Increase the stack from 256 to 4096 bytes to avoid overflow and
increase the stack entry type size to accomodate 8MB+ PSRAM.
Changes are:
- ports/rp2/mpconfigport.h: Make split-heap optional and enable by default.
- ports/rp2/mpconfigport.h: Increase GC stack entry type to uint32_t.
- ports/rp2/mpconfigport.h: Raise GC stack size.
Co-authored-by: Kirk Benell <kirk.benell@sparkfun.com>
Signed-off-by: Phil Howard <github@gadgetoid.com>
Performs a best-effort attempt to detect attached PSRAM, configure it and
*add* it to the MicroPython heap. If PSRAM is not present, should fall
back to use internal RAM.
Introduce two new port/board defines:
- MICROPY_HW_ENABLE_PSRAM to enable PSRAM.
- MICROPY_HW_PSRAM_CS_PIN to define the chip-select pin (required).
Changes are:
- ports/rp2/rp2_psram.[ch]: Add new PSRAM module.
- ports/rp2/main.c: Add optional PSRAM support.
- ports/rp2/CMakeLists.txt: Include rp2_psram.c.
- ports/rp2/mpconfigport.h: Add MICROPY_HW_ENABLE_PSRAM.
- ports/rp2/modmachine.c: Reconfigure PSRAM on freq change.
Co-authored-by: Kirk Benell <kirk.benell@sparkfun.com>
Co-authored-by: Mike Bell <mike@mercuna.com>
Signed-off-by: Phil Howard <phil@gadgetoid.com>
This commit removes a definition used back when ESP-IDF v4 was supported
by MicroPython. Those times are now long gone, and so is the need for
that particular definition to be set in the first place.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit cleans up a couple of RISC-V specific directives in the
build script. Namely, removes the forced inclusion of the "riscv"
component and introduces proper mpy-cross flags.
The "riscv" component is already included by the ESP-IDF build
framework, as certain low-level components would not build otherwise, so
there is no need to add it to the required components list.
The architecture flag for mpy-cross is now set for RISC-V targets, as it
was previously set only for Xtensa targets (and it relied on a string
comparison rather than using the appropriate configuration variable).
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit changes the gchelper implementation in use for RV32-based
targets (ESP32C3, ESP32C6) from the generic one written in C to the one
written in assembler that is specific to the CPU in question.
The native implementation is already exercised on most CI builds as it
is used by the QEMU port to compile and test the RV32 target.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
The PYBD boards use an F7xx which has an errata 2.4.3:
Memory-mapped read operations may fail when timeout counter is enabled
This is unfortunate because it means that once QSPI memory-mapped flash is
accessed the QSPI peripheral will leave the CS pin active (low) forever,
which increases power consumption of the SPI flash chip (because it's
active and waiting for commands). The exact amount of power increase
depends on the flash, but the PYBD_SFx increase by about 2.5mA.
Previously this increase in power only happened when QSPI flash was needed,
eg on PYBD_SF2 when mbedtls or nimble libraries were used. On PYBD_SF6
it's actually never used.
But with the introduction of ROMFS which lives in the QSPI flash, the
memory is always access on start up to see if the ROMFS contains a valid
image (it must read the memory to find out). That means these boards
always consume about 2.5mA more after starting up (compared to when ROMFS
is disabled).
The fix in this commit is to explicitly restart the QSPI memory mapped mode
during the start up process. More precisely, the restart is done after
querying the ROMFS and just before trying to execute `boot.py`. That's the
right location to keep power consumption permanently down if the QSPI is
never used (eg ROMFS image doesn't exist).
Signed-off-by: Damien George <damien@micropython.org>
