The right service call to get UID is SERVICES_system_get_eui_extension
which returns an 8 bytes UID.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The byte order (endianness) seems to be swapped when read in 8D-8D-8D in
XIP mode, for most flashes, with the exception of MX which seems to swap
half-words.
This commit adds a flash setting to allow parts to enable half-word swap
when data is written, to fix this issue. By default, only endianness is
fixed.
Tested with both MX and ISSI parts on AE3, flash test and simple file
write/read.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The OSPI controller supports concurrent direct/XIP accesses, there's no
need to disable XIP on direct access. In addition to improving the
performance, this change lays the groundwork for supporting access by
the HP and HE cores simultaneously.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This change increases XIP read speed to ~30Mbytes/s at 50MHz DDR:
- Enable continuous mode.
- Remove hard-coded settings.
- Set XIP continuous mode timeout.
The prefetch remains disabled. Although enabling the prefetch gives the
best performance for the CPU in XIP mode, it must be disabled when the NPU
accesses the OSPI flash.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Leaving this pin low in combination with the default EM settings enables
flash protection for the EM flash.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The default dummy cycles may not match the actual flash frequency supported
by a certain board. For example, the MX chip uses 20 dummy cycles by
default which supports up to 200MHz DDR, but the maximum frequency
supported by the AE3 board is 50MHz DDR. So the dummy cycles for this
board can be as low as 6. It's important to set the correct dummy cycles,
as it results in doubling the XIP read speed, in the case of the AE3 board.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit enables detecting the flash device in runtime, and uses the
settings of the detected device instead of board-defined flash settings.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The same MicroPython firmware is built for the HE but with slightly
different options, for example no USB.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
With this new Makefile you can build the following:
make BOARD=MY_BOARD MCU_CORE=M55_HP # build HP firmware/ToC.
make BOARD=MY_BOARD MCU_CORE=M55_HE # build HE firmware/ToC.
make BOARD=MY_BOARD MCU_CORE=M55_DUAL # build HE+HP firmware + ToC.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Includes services to get random numbers, reset SoC, get unique-id, dump SoC
info, and CPU control services.
Signed-off-by: Damien George <damien@micropython.org>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit adds the beginning of a new alif port with support for Alif
Ensemble MCUs. See https://alifsemi.com/
Supported features of this port added by this commit:
- UART REPL.
- TinyUSB support, for REPL and MSC.
- Octal SPI flash support, for filesystem.
- machine.Pin support.
General notes about the port:
- It uses make, similar to other bare-metal ports here.
- The toolchain is the standard arm-none-eabi- toolchain.
- Flashing a board can be done using either the built-in serial bootloader,
or JLink (both supported here).
- There are two required submodules (one for drivers/SDK, one for security
tools), both of which are open source and on GitHub.
- No special hardware or software is needed for development, just a board
connected over USB.
OpenMV have generously sponsored the development of this port.
Signed-off-by: Damien George <damien@micropython.org>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
The cyw43-driver now provides the Bluetooth initialisation code, making
`drivers/cyw43/cywbt.c` obsolete. To use the new code a port must enable
the `CYW43_ENABLE_BLUETOOTH_OVER_UART` option.
Some ports have yet to migrate to the new code, so in the meantime they can
explicitly add the old source to their source list and continue to use it
without change.
Signed-off-by: Damien George <damien@micropython.org>
This file is part of the updated cyw43-driver. It will only be used if
`CYW43_USE_SPI` is enabled.
Signed-off-by: Damien George <damien@micropython.org>
Configure flash timings dynamically to match the system clock. Reconfigure
timings after flash writes.
Changes are:
- ports/rp2/main.c: Set default flash timings.
- ports/rp2/modmachine.c: Configure optimal flash timings on freq change.
- ports/rp2/rp2_flash.c: Reconfigure flash when leaving critical section.
Signed-off-by: Phil Howard <github@gadgetoid.com>
Add a 256 byte (FLASH_PAGE_SIZE) SRAM copy buffer to allow copies from
PSRAM to flash. This would otherwise hardfault since PSRAM is disabled
when doing a write to flash.
Changes are:
- ports/rp2/rp2_flash.c: Add 256 byte (flash page size) SRAM copy buffer
for PSRAM to flash copies.
- ports/rp2/rp2_flash.c: Invalidate the XIP cache to purge any PSRAM
data before critical flash operations.
Co-authored-by: Phil Howard <github@gadgetoid.com>
Co-authored-by: Angus Gratton <angus@redyak.com.au>
Signed-off-by: Phil Howard <github@gadgetoid.com>
