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support for Airmont
This commit is contained in:
Andreas Abel
212
configs/cfg_Silvermont_all_core.txt
Normal file
212
configs/cfg_Silvermont_all_core.txt
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@@ -0,0 +1,212 @@
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# Based on https://download.01.org/perfmon/SLM/Silvermont_core_V14.json
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# Applies to processors with family-model in {6-37, 6-4D, 6-4C}
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# Loads blocked due to store forward restriction
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03.01 REHABQ.LD_BLOCK_ST_FORWARD
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# Loads blocked due to store data not ready
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03.02 REHABQ.LD_BLOCK_STD_NOTREADY
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# Store uops that split cache line boundary
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03.04 REHABQ.ST_SPLITS
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# Load uops that split cache line boundary
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03.08 REHABQ.LD_SPLITS
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# Uops with lock semantics
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03.10 REHABQ.LOCK
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# Store address buffer full
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03.20 REHABQ.STA_FULL
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# Any reissued load uops
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03.40 REHABQ.ANY_LD
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# Any reissued store uops
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03.80 REHABQ.ANY_ST
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# Loads missed L1
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04.01 MEM_UOPS_RETIRED.L1_MISS_LOADS
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# Loads hit L2
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04.02 MEM_UOPS_RETIRED.L2_HIT_LOADS
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# Loads missed L2
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04.04 MEM_UOPS_RETIRED.L2_MISS_LOADS
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# Loads missed DTLB
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04.08 MEM_UOPS_RETIRED.DTLB_MISS_LOADS
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# Loads missed UTLB
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04.10 MEM_UOPS_RETIRED.UTLB_MISS
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# Cross core or cross module hitm
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04.20 MEM_UOPS_RETIRED.HITM
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# All Loads
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04.40 MEM_UOPS_RETIRED.ALL_LOADS
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# All Stores
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04.80 MEM_UOPS_RETIRED.ALL_STORES
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# Duration of D-side page-walks in core cycles
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05.01 PAGE_WALKS.D_SIDE_CYCLES
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# D-side page-walks
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05.01.EDG PAGE_WALKS.D_SIDE_WALKS
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# Duration of I-side page-walks in core cycles
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05.02 PAGE_WALKS.I_SIDE_CYCLES
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# I-side page-walks
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05.02.EDG PAGE_WALKS.I_SIDE_WALKS
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# Total cycles for all the page walks. (I-side and D-side)
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05.03 PAGE_WALKS.CYCLES
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# Total page walks that are completed (I-side and D-side)
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05.03.EDG PAGE_WALKS.WALKS
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# L2 cache request misses
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2E.41 LONGEST_LAT_CACHE.MISS
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# L2 cache requests from this core
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2E.4F LONGEST_LAT_CACHE.REFERENCE
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# Counts the number of request from the L2 that were not accepted into the XQ
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30.00 L2_REJECT_XQ.ALL
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# Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.
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31.00 CORE_REJECT_L2Q.ALL
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# Core cycles when core is not halted
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3C.00 CPU_CLK_UNHALTED.CORE_P
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# Reference cycles when core is not halted
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3C.01 CPU_CLK_UNHALTED.REF
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# Instruction fetches from Icache
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80.01 ICACHE.HIT
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# Icache miss
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80.02 ICACHE.MISSES
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# Instruction fetches
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80.03 ICACHE.ACCESSES
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# Cycles code-fetch stalled due to an outstanding ITLB miss.
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86.02 FETCH_STALL.ITLB_FILL_PENDING_CYCLES
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# Cycles code-fetch stalled due to an outstanding ICache miss.
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86.04 FETCH_STALL.ICACHE_FILL_PENDING_CYCLES
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# Cycles code-fetch stalled due to any reason.
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86.3F FETCH_STALL.ALL
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# Instructions retired
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C0.00 INST_RETIRED.ANY_P
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# MSROM micro-ops retired
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C2.01 UOPS_RETIRED.MS
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# Micro-ops retired
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C2.10 UOPS_RETIRED.ALL
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# Self-Modifying Code detected
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C3.01 MACHINE_CLEARS.SMC
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# Stalls due to Memory ordering
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C3.02 MACHINE_CLEARS.MEMORY_ORDERING
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# Stalls due to FP assists
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C3.04 MACHINE_CLEARS.FP_ASSIST
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# Counts all machine clears
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C3.08 MACHINE_CLEARS.ALL
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# Counts the number of branch instructions retired...
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C4.00 BR_INST_RETIRED.ALL_BRANCHES
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# Counts the number of JCC branch instructions retired
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C4.7E BR_INST_RETIRED.JCC
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# Counts the number of taken branch instructions retired
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C4.80 BR_INST_RETIRED.ALL_TAKEN_BRANCHES
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# Counts the number of far branch instructions retired
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C4.BF BR_INST_RETIRED.FAR_BRANCH
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# Counts the number of near indirect JMP and near indirect CALL branch instructions retired
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C4.EB BR_INST_RETIRED.NON_RETURN_IND
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# Counts the number of near RET branch instructions retired
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C4.F7 BR_INST_RETIRED.RETURN
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# Counts the number of near CALL branch instructions retired
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C4.F9 BR_INST_RETIRED.CALL
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# Counts the number of near indirect CALL branch instructions retired
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C4.FB BR_INST_RETIRED.IND_CALL
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# Counts the number of near relative CALL branch instructions retired
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C4.FD BR_INST_RETIRED.REL_CALL
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# Counts the number of taken JCC branch instructions retired
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C4.FE BR_INST_RETIRED.TAKEN_JCC
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# Counts the number of mispredicted branch instructions retired
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C5.00 BR_MISP_RETIRED.ALL_BRANCHES
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# Counts the number of mispredicted JCC branch instructions retired
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C5.7E BR_MISP_RETIRED.JCC
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# Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired
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C5.EB BR_MISP_RETIRED.NON_RETURN_IND
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# Counts the number of mispredicted near RET branch instructions retired
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C5.F7 BR_MISP_RETIRED.RETURN
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# Counts the number of mispredicted near indirect CALL branch instructions retired
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C5.FB BR_MISP_RETIRED.IND_CALL
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# Counts the number of mispredicted taken JCC branch instructions retired
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C5.FE BR_MISP_RETIRED.TAKEN_JCC
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# Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)
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CA.01 NO_ALLOC_CYCLES.ROB_FULL
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# Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted
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CA.04 NO_ALLOC_CYCLES.MISPREDICTS
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# Counts the number of cycles when no uops are allocated and a RATstall is asserted.
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CA.20 NO_ALLOC_CYCLES.RAT_STALL
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# Counts the number of cycles when no uops are allocated for any reason.
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CA.3F NO_ALLOC_CYCLES.ALL
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# Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.
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CA.50 NO_ALLOC_CYCLES.NOT_DELIVERED
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# Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M
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CB.01 RS_FULL_STALL.MEC
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# Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.
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CB.1F RS_FULL_STALL.ALL
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# Cycles the divider is busy. Does not imply a stall waiting for the divider.
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CD.01 CYCLES_DIV_BUSY.ALL
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# Counts the number of baclears
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E6.01 BACLEARS.ALL
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# Counts the number of RETURN baclears
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E6.08 BACLEARS.RETURN
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# Counts the number of JCC baclears
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E6.10 BACLEARS.COND
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# Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count.
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E7.01 MS_DECODED.MS_ENTRY
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# Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction
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E9.01 DECODE_RESTRICTION.PREDECODE_WRONG
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170
configs/cfg_Silvermont_all_offcore.txt
Normal file
170
configs/cfg_Silvermont_all_offcore.txt
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@@ -0,0 +1,170 @@
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# Based on https://download.01.org/perfmon/SLM/Silvermont_core_V14.json
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# Applies to processors with family-model in {6-37, 6-4D, 6-4C}
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# Counts demand and DCU prefetch data read that have any response type.
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B7.01.MSR_RSP0=0x0000010001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE
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# Counts demand and DCU prefetch instruction cacheline that have any response type.
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B7.01.MSR_RSP0=0x0000010004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE
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# Counts any rfo reads (demand & prefetch) that have any response type.
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B7.01.MSR_RSP0=0x0000010022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE
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# Counts any code reads (demand & prefetch) that have any response type.
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B7.01.MSR_RSP0=0x0000010044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE
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# Counts DCU hardware prefetcher data read that have any response type.
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B7.01.MSR_RSP0=0x0000012000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE
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# Counts any data read (demand & prefetch) that have any response type.
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B7.01.MSR_RSP0=0x0000013091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE
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# Counts any request that have any response type.
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B7.01.MSR_RSP0=0x0000018008.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE
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# Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.
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B7.01.MSR_RSP0=0x0080000008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED
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# Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS
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# Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS
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# Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS
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# Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS
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# Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS
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# Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS
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# Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000040.TakenAlone OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS
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# Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS
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# Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS
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# Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS
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# Counts any request that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200008008.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS
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# Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000040.TakenAlone OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
|
||||
B7.01.MSR_RSP0=0x0400003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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||||
B7.01.MSR_RSP0=0x0400008008.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD
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||||
# Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.
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||||
B7.01.MSR_RSP0=0x1000000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE
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||||
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# Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.
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||||
B7.01.MSR_RSP0=0x1000000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE
|
||||
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||||
# Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE
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||||
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||||
# Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.
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||||
B7.01.MSR_RSP0=0x1000000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE
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||||
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||||
# Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE
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||||
# Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.
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||||
B7.01.MSR_RSP0=0x1000000044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE
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||||
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||||
# Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.
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||||
B7.01.MSR_RSP0=0x1000002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE
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||||
|
||||
# Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.
|
||||
B7.01.MSR_RSP0=0x1000003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE
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||||
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||||
# Counts any request that hit in the other module where modified copies were found in other core's L1 cache.
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||||
B7.01.MSR_RSP0=0x1000008008.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE
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||||
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||||
# Counts demand and DCU prefetch data read that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY
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||||
|
||||
# Counts demand and DCU prefetch RFOs that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY
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||||
|
||||
# Counts demand and DCU prefetch instruction cacheline that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY
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||||
|
||||
# Counts writeback (modified to exclusive) that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_MISS.ANY
|
||||
|
||||
# Counts data cacheline reads generated by L2 prefetchers that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY
|
||||
|
||||
# Counts RFO requests generated by L2 prefetchers that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY
|
||||
|
||||
# Counts any rfo reads (demand & prefetch) that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY
|
||||
|
||||
# Counts code reads generated by L2 prefetchers that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000040.TakenAlone OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY
|
||||
|
||||
# Counts any code reads (demand & prefetch) that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY
|
||||
|
||||
# Counts demand reads of partial cache lines (including UC and WC) that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000080.TakenAlone OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY
|
||||
|
||||
# Countsof demand RFO requests to write to partial cache lines that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680000100.TakenAlone OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY
|
||||
|
||||
# Counts DCU hardware prefetcher data read that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY
|
||||
|
||||
# Counts any data read (demand & prefetch) that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY
|
||||
|
||||
# Counts streaming store that miss L2.
|
||||
B7.01.MSR_RSP0=0x1680004800.TakenAlone OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY
|
||||
|
||||
# Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.
|
||||
B7.01.MSR_RSP0=0x4000000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING
|
||||
|
||||
# Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.
|
||||
B7.01.MSR_RSP0=0x4000000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING
|
||||
|
||||
# Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.
|
||||
B7.01.MSR_RSP0=0x4000000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING
|
||||
14
configs/cfg_Silvermont_common.txt
Normal file
14
configs/cfg_Silvermont_common.txt
Normal file
@@ -0,0 +1,14 @@
|
||||
# Based on https://download.01.org/perfmon/SLM/Silvermont_core_V14.json
|
||||
# Applies to processors with family-model in {6-37, 6-4D, 6-4C}
|
||||
|
||||
3C.00 CORE_CYCLES
|
||||
C0.00 INST_RETIRED
|
||||
C2.10 UOPS_RETIRED.ALL
|
||||
C2.01 UOPS_RETIRED.MS
|
||||
C4.00 BR_INST_RETIRED.ALL_BRANCHES
|
||||
C5.00 BR_MISP_RETIRED.ALL_BRANCHES
|
||||
04.40 MEM_UOPS_RETIRED.ALL_LOADS
|
||||
04.80 MEM_UOPS_RETIRED.ALL_STORES
|
||||
04.01 MEM_UOPS_RETIRED.L1_MISS_LOADS
|
||||
04.02 MEM_UOPS_RETIRED.L2_HIT_LOADS
|
||||
04.04 MEM_UOPS_RETIRED.L2_MISS_LOADS
|
||||
@@ -213,8 +213,10 @@ def micro_arch(cpu):
|
||||
return 'HSX'
|
||||
if (vi.displ_family, vi.displ_model) in [(0x06, 0x3D), (0x06, 0x47), (0x06, 0x56), (0x06, 0x4F)]:
|
||||
return 'BDW'
|
||||
if (vi.displ_family, vi.displ_model) in [(0x06, 0x37), (0x06, 0x4C), (0x06, 0x4D)]:
|
||||
if (vi.displ_family, vi.displ_model) in [(0x06, 0x37), (0x06, 0x4D)]:
|
||||
return 'SLM'
|
||||
if (vi.displ_family, vi.displ_model) in [(0x06, 0x4C)]:
|
||||
return 'AMT'
|
||||
if (vi.displ_family, vi.displ_model) in [(0x06, 0x5C), (0x06, 0x5F)]:
|
||||
return 'GLM'
|
||||
if (vi.displ_family, vi.displ_model) in [(0x06, 0x57)]:
|
||||
|
||||
@@ -209,7 +209,7 @@ def runExperiment(instrNode, instrCode, init=None, unrollCount=500, loopCount=0,
|
||||
if evt == 'UOPS':
|
||||
if arch in ['CON', 'WOL']: evt = 'RS_UOPS_DISPATCHED'
|
||||
elif arch in ['NHM', 'WSM', 'BNL', 'GLM', 'GLP']: evt = 'UOPS_RETIRED.ANY'
|
||||
elif arch in ['SNB', 'ADL-E']: evt = 'UOPS_RETIRED.ALL'
|
||||
elif arch in ['SNB', 'SLM', 'AMT', 'ADL-E']: evt = 'UOPS_RETIRED.ALL'
|
||||
elif arch in ['HSW']: evt = 'UOPS_EXECUTED.CORE'
|
||||
elif arch in ['IVB', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX', 'TGL', 'RKL', 'ADL-P']: evt = 'UOPS_EXECUTED.THREAD'
|
||||
localHtmlReports.append('<li>' + evt + ': ' + str(value) + '</li>\n')
|
||||
@@ -276,7 +276,7 @@ def getEventConfig(event):
|
||||
if arch in ['NHM', 'WSM', 'SNB' ]: return 'C2.01' # UOPS_RETIRED.ANY
|
||||
if arch in ['SNB']: return 'C2.01' # UOPS_RETIRED.ALL
|
||||
if arch in ['GLM', 'GLP', 'ADL-E']: return 'C2.00' # UOPS_RETIRED.ALL
|
||||
if arch in ['BNL']: return 'C2.10' # UOPS_RETIRED.ANY
|
||||
if arch in ['BNL', 'SLM', 'AMT']: return 'C2.10' # UOPS_RETIRED.ANY
|
||||
if arch in ['HSW']: return 'B1.02' # UOPS_EXECUTED.CORE; note: may undercount due to erratum HSD30
|
||||
if arch in ['IVB', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX', 'TGL', 'RKL', 'ADL-P']: return 'B1.01' # UOPS_EXECUTED.THREAD
|
||||
if arch in ['ZEN+', 'ZEN2', 'ZEN3']: return '0C1.00'
|
||||
@@ -290,7 +290,7 @@ def getEventConfig(event):
|
||||
if arch in ['NHM', 'WSM']: return 'D1.02'
|
||||
if arch in ['SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX', 'TGL', 'RKL']: return '79.30'
|
||||
if arch in ['ADL-P']: return '79.20'
|
||||
if arch in ['GLM', 'GLP', 'ADL-E']: return 'C2.01'
|
||||
if arch in ['SLM', 'AMT', 'GLM', 'GLP', 'ADL-E']: return 'C2.01'
|
||||
if arch in ['BNL']: return 'A9.01' # undocumented, but seems to work
|
||||
if event == 'UOPS_PORT_0':
|
||||
if arch in ['CON', 'WOL']: return 'A1.01.CTR=0'
|
||||
|
||||
Reference in New Issue
Block a user