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https://github.com/andreas-abel/nanoBench.git
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interrupts
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@@ -506,6 +506,7 @@ uint32_t prev_LVTPC = 0;
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uint32_t prev_LVT0 = 0;
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uint32_t prev_LVT1 = 0;
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uint32_t prev_LVTERR = 0;
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uint32_t prev_APIC_TMICT = 0;
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uint64_t prev_deadline = 0;
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static void restore_interrupts_preemption(void) {
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@@ -515,8 +516,12 @@ static void restore_interrupts_preemption(void) {
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apic_write(APIC_LVT0, prev_LVT0);
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apic_write(APIC_LVT1, prev_LVT1);
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apic_write(APIC_LVTERR, prev_LVTERR);
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if (supports_tsc_deadline) write_msr(MSR_IA32_TSC_DEADLINE, prev_deadline);
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prev_LVTT = prev_LVTTHMR = prev_LVTPC = prev_LVT0 = prev_LVT1 = prev_LVTERR = prev_deadline = 0;
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apic_write(APIC_TMICT, prev_APIC_TMICT);
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if (supports_tsc_deadline) {
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asm volatile("mfence");
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write_msr(MSR_IA32_TSC_DEADLINE, max(1ULL, prev_deadline));
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}
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prev_LVTT = prev_LVTTHMR = prev_LVTPC = prev_LVT0 = prev_LVT1 = prev_LVTERR = prev_APIC_TMICT = prev_deadline = 0;
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put_cpu();
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}
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@@ -539,7 +544,11 @@ static void disable_interrupts_preemption(void) {
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prev_LVT0 = apic_read(APIC_LVT0);
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prev_LVT1 = apic_read(APIC_LVT1);
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prev_LVTERR = apic_read(APIC_LVTERR);
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if (supports_tsc_deadline) prev_deadline = read_msr(MSR_IA32_TSC_DEADLINE);
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prev_APIC_TMICT = apic_read(APIC_TMICT);
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if (supports_tsc_deadline) {
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prev_deadline = read_msr(MSR_IA32_TSC_DEADLINE);
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write_msr(MSR_IA32_TSC_DEADLINE, 0);
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}
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apic_write(APIC_LVTT, prev_LVTT | APIC_LVT_MASKED);
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apic_write(APIC_LVTTHMR, prev_LVTTHMR | APIC_LVT_MASKED);
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