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213 lines
6.2 KiB
Plaintext
213 lines
6.2 KiB
Plaintext
# Based on https://download.01.org/perfmon/SLM/Silvermont_core_V14.json
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# Applies to processors with family-model in {6-37, 6-4D, 6-4C}
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# Loads blocked due to store forward restriction
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03.01 REHABQ.LD_BLOCK_ST_FORWARD
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# Loads blocked due to store data not ready
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03.02 REHABQ.LD_BLOCK_STD_NOTREADY
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# Store uops that split cache line boundary
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03.04 REHABQ.ST_SPLITS
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# Load uops that split cache line boundary
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03.08 REHABQ.LD_SPLITS
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# Uops with lock semantics
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03.10 REHABQ.LOCK
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# Store address buffer full
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03.20 REHABQ.STA_FULL
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# Any reissued load uops
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03.40 REHABQ.ANY_LD
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# Any reissued store uops
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03.80 REHABQ.ANY_ST
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# Loads missed L1
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04.01 MEM_UOPS_RETIRED.L1_MISS_LOADS
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# Loads hit L2
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04.02 MEM_UOPS_RETIRED.L2_HIT_LOADS
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# Loads missed L2
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04.04 MEM_UOPS_RETIRED.L2_MISS_LOADS
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# Loads missed DTLB
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04.08 MEM_UOPS_RETIRED.DTLB_MISS_LOADS
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# Loads missed UTLB
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04.10 MEM_UOPS_RETIRED.UTLB_MISS
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# Cross core or cross module hitm
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04.20 MEM_UOPS_RETIRED.HITM
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# All Loads
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04.40 MEM_UOPS_RETIRED.ALL_LOADS
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# All Stores
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04.80 MEM_UOPS_RETIRED.ALL_STORES
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# Duration of D-side page-walks in core cycles
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05.01 PAGE_WALKS.D_SIDE_CYCLES
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# D-side page-walks
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05.01.EDG PAGE_WALKS.D_SIDE_WALKS
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# Duration of I-side page-walks in core cycles
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05.02 PAGE_WALKS.I_SIDE_CYCLES
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# I-side page-walks
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05.02.EDG PAGE_WALKS.I_SIDE_WALKS
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# Total cycles for all the page walks. (I-side and D-side)
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05.03 PAGE_WALKS.CYCLES
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# Total page walks that are completed (I-side and D-side)
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05.03.EDG PAGE_WALKS.WALKS
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# L2 cache request misses
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2E.41 LONGEST_LAT_CACHE.MISS
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# L2 cache requests from this core
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2E.4F LONGEST_LAT_CACHE.REFERENCE
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# Counts the number of request from the L2 that were not accepted into the XQ
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30.00 L2_REJECT_XQ.ALL
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# Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.
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31.00 CORE_REJECT_L2Q.ALL
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# Core cycles when core is not halted
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3C.00 CPU_CLK_UNHALTED.CORE_P
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# Reference cycles when core is not halted
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3C.01 CPU_CLK_UNHALTED.REF
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# Instruction fetches from Icache
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80.01 ICACHE.HIT
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# Icache miss
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80.02 ICACHE.MISSES
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# Instruction fetches
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80.03 ICACHE.ACCESSES
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# Cycles code-fetch stalled due to an outstanding ITLB miss.
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86.02 FETCH_STALL.ITLB_FILL_PENDING_CYCLES
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# Cycles code-fetch stalled due to an outstanding ICache miss.
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86.04 FETCH_STALL.ICACHE_FILL_PENDING_CYCLES
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# Cycles code-fetch stalled due to any reason.
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86.3F FETCH_STALL.ALL
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# Instructions retired
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C0.00 INST_RETIRED.ANY_P
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# MSROM micro-ops retired
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C2.01 UOPS_RETIRED.MS
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# Micro-ops retired
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C2.10 UOPS_RETIRED.ALL
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# Self-Modifying Code detected
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C3.01 MACHINE_CLEARS.SMC
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# Stalls due to Memory ordering
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C3.02 MACHINE_CLEARS.MEMORY_ORDERING
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# Stalls due to FP assists
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C3.04 MACHINE_CLEARS.FP_ASSIST
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# Counts all machine clears
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C3.08 MACHINE_CLEARS.ALL
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# Counts the number of branch instructions retired...
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C4.00 BR_INST_RETIRED.ALL_BRANCHES
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# Counts the number of JCC branch instructions retired
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C4.7E BR_INST_RETIRED.JCC
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# Counts the number of taken branch instructions retired
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C4.80 BR_INST_RETIRED.ALL_TAKEN_BRANCHES
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# Counts the number of far branch instructions retired
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C4.BF BR_INST_RETIRED.FAR_BRANCH
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# Counts the number of near indirect JMP and near indirect CALL branch instructions retired
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C4.EB BR_INST_RETIRED.NON_RETURN_IND
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# Counts the number of near RET branch instructions retired
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C4.F7 BR_INST_RETIRED.RETURN
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# Counts the number of near CALL branch instructions retired
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C4.F9 BR_INST_RETIRED.CALL
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# Counts the number of near indirect CALL branch instructions retired
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C4.FB BR_INST_RETIRED.IND_CALL
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# Counts the number of near relative CALL branch instructions retired
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C4.FD BR_INST_RETIRED.REL_CALL
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# Counts the number of taken JCC branch instructions retired
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C4.FE BR_INST_RETIRED.TAKEN_JCC
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# Counts the number of mispredicted branch instructions retired
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C5.00 BR_MISP_RETIRED.ALL_BRANCHES
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# Counts the number of mispredicted JCC branch instructions retired
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C5.7E BR_MISP_RETIRED.JCC
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# Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired
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C5.EB BR_MISP_RETIRED.NON_RETURN_IND
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# Counts the number of mispredicted near RET branch instructions retired
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C5.F7 BR_MISP_RETIRED.RETURN
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# Counts the number of mispredicted near indirect CALL branch instructions retired
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C5.FB BR_MISP_RETIRED.IND_CALL
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# Counts the number of mispredicted taken JCC branch instructions retired
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C5.FE BR_MISP_RETIRED.TAKEN_JCC
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# Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)
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CA.01 NO_ALLOC_CYCLES.ROB_FULL
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# Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted
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CA.04 NO_ALLOC_CYCLES.MISPREDICTS
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# Counts the number of cycles when no uops are allocated and a RATstall is asserted.
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CA.20 NO_ALLOC_CYCLES.RAT_STALL
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# Counts the number of cycles when no uops are allocated for any reason.
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CA.3F NO_ALLOC_CYCLES.ALL
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# Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.
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CA.50 NO_ALLOC_CYCLES.NOT_DELIVERED
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# Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M
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CB.01 RS_FULL_STALL.MEC
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# Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.
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CB.1F RS_FULL_STALL.ALL
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# Cycles the divider is busy. Does not imply a stall waiting for the divider.
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CD.01 CYCLES_DIV_BUSY.ALL
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# Counts the number of baclears
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E6.01 BACLEARS.ALL
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# Counts the number of RETURN baclears
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E6.08 BACLEARS.RETURN
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# Counts the number of JCC baclears
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E6.10 BACLEARS.COND
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# Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count.
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E7.01 MS_DECODED.MS_ENTRY
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# Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction
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E9.01 DECODE_RESTRICTION.PREDECODE_WRONG
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