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171 lines
10 KiB
Plaintext
171 lines
10 KiB
Plaintext
# Based on https://download.01.org/perfmon/SLM/Silvermont_core_V14.json
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# Applies to processors with family-model in {6-37, 6-4D, 6-4C}
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# Counts demand and DCU prefetch data read that have any response type.
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B7.01.MSR_RSP0=0x0000010001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE
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# Counts demand and DCU prefetch instruction cacheline that have any response type.
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B7.01.MSR_RSP0=0x0000010004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE
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# Counts any rfo reads (demand & prefetch) that have any response type.
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B7.01.MSR_RSP0=0x0000010022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE
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# Counts any code reads (demand & prefetch) that have any response type.
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B7.01.MSR_RSP0=0x0000010044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE
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# Counts DCU hardware prefetcher data read that have any response type.
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B7.01.MSR_RSP0=0x0000012000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE
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# Counts any data read (demand & prefetch) that have any response type.
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B7.01.MSR_RSP0=0x0000013091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE
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# Counts any request that have any response type.
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B7.01.MSR_RSP0=0x0000018008.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE
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# Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.
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B7.01.MSR_RSP0=0x0080000008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED
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# Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS
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# Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS
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# Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS
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# Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS
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# Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS
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# Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS
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# Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000040.TakenAlone OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS
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# Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200000044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS
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# Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS
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# Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS
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# Counts any request that miss L2 with a snoop miss response.
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B7.01.MSR_RSP0=0x0200008008.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS
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# Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000040.TakenAlone OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400000044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
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B7.01.MSR_RSP0=0x0400008008.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD
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# Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE
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# Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE
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# Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE
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# Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE
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# Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE
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# Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000000044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE
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# Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE
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# Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE
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# Counts any request that hit in the other module where modified copies were found in other core's L1 cache.
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B7.01.MSR_RSP0=0x1000008008.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE
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# Counts demand and DCU prefetch data read that miss L2.
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B7.01.MSR_RSP0=0x1680000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY
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# Counts demand and DCU prefetch RFOs that miss L2.
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B7.01.MSR_RSP0=0x1680000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY
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# Counts demand and DCU prefetch instruction cacheline that miss L2.
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B7.01.MSR_RSP0=0x1680000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY
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# Counts writeback (modified to exclusive) that miss L2.
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B7.01.MSR_RSP0=0x1680000008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_MISS.ANY
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# Counts data cacheline reads generated by L2 prefetchers that miss L2.
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B7.01.MSR_RSP0=0x1680000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY
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# Counts RFO requests generated by L2 prefetchers that miss L2.
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B7.01.MSR_RSP0=0x1680000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY
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# Counts any rfo reads (demand & prefetch) that miss L2.
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B7.01.MSR_RSP0=0x1680000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY
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# Counts code reads generated by L2 prefetchers that miss L2.
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B7.01.MSR_RSP0=0x1680000040.TakenAlone OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY
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# Counts any code reads (demand & prefetch) that miss L2.
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B7.01.MSR_RSP0=0x1680000044.TakenAlone OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY
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# Counts demand reads of partial cache lines (including UC and WC) that miss L2.
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B7.01.MSR_RSP0=0x1680000080.TakenAlone OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY
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# Countsof demand RFO requests to write to partial cache lines that miss L2.
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B7.01.MSR_RSP0=0x1680000100.TakenAlone OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY
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# Counts DCU hardware prefetcher data read that miss L2.
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B7.01.MSR_RSP0=0x1680002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY
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# Counts any data read (demand & prefetch) that miss L2.
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B7.01.MSR_RSP0=0x1680003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY
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# Counts streaming store that miss L2.
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B7.01.MSR_RSP0=0x1680004800.TakenAlone OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY
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# Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.
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B7.01.MSR_RSP0=0x4000000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING
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# Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.
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B7.01.MSR_RSP0=0x4000000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING
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# Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.
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B7.01.MSR_RSP0=0x4000000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING
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