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80ae3a6036faa7cc8d7fe7bfb3945f28a0af350f
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Author SHA1 Message Date
Julian Hammer
80ae3a6036 Merge branch 'master' of github.com:RRZE-HPC/asmbench 2019-07-17 11:53:08 +02:00
Julian Hammer
242daeead3 increased parallel factor for load tp benchmark 2019-07-17 11:52:31 +02:00
Julian Hammer
79544033f0 graceful failing IACA analysis errors with -vvv 2019-07-16 13:22:08 +02:00
Julian Hammer
a89a96046f some frequency fixes 2019-07-16 10:20:24 +02:00
Julian Hammer
164eb03bf4 added (-f|--frequency) argument to cli of oldjit and asmbench 2019-07-16 09:38:42 +02:00
Julian Hammer
0e8157c594 fixed LD LAT result metric problem 2019-07-15 18:02:20 +02:00
Julian Hammer
7961659d85 adde console script asmbench 2019-02-01 13:49:18 +01:00
Julian Hammer
d218b55a50 better error message 2019-02-01 10:50:44 +01:00
Julian Hammer
f3ed5a0695 added sc18 src poster and summary 2019-01-17 13:41:20 +01:00
Julian Hammer
dd882088da removed irrelevant test files v0.1.2 2018-09-25 12:34:37 +02:00
Julian Hammer
54c485576f readded lost folder 2018-09-25 12:33:27 +02:00
Julian Hammer
5f3217c59f final commit for poster publication 2018-09-25 10:55:07 +02:00
Julian Hammer
21fb4d1c4d changed to rst readme 2018-09-25 10:37:53 +02:00
Julian Hammer
2cd25b4bcd added manifest file 2018-09-25 10:31:23 +02:00
Julian Hammer
dbbd37585a renamed to asmbench 2018-09-25 10:23:40 +02:00
Julian
3033246d4e Create sc18src_artifact_appendix.md 2018-09-17 16:04:33 +02:00
Julian Hammer
515b28cb4e added src extras 2018-08-02 10:49:49 +02:00
Julian Hammer
c5f82d8ec2 reordered instructions 2018-07-30 10:04:03 +02:00
Julian Hammer
0f6c440421 added div to benchmark 2018-07-30 10:02:07 +02:00
Julian Hammer
6172203aaf made repeat and elapstime configurable 2018-07-30 09:53:13 +02:00
Julian Hammer
cc51b232c2 workaround from ryzen / xen - llvm bug 2018-07-27 16:44:43 +02:00
Julian Hammer
d9bc86456d IACA report now available with -vvv 2018-07-27 14:40:16 +02:00
Julian Hammer
60ed2d2877 added zero runtime handling 2018-07-27 12:43:52 +02:00
Julian Hammer
e4c5b66741 handling overflow error in argument preperation 2018-07-27 12:30:18 +02:00
Julian Hammer
50c4da06f6 updated output 2018-07-27 11:00:22 +02:00
Julian Hammer
0dbf6b655b updated parameters 2018-07-26 16:35:32 +02:00
Julian Hammer
55ac8a142d added initial SRC script 2018-07-26 16:03:34 +02:00
Julian Hammer
6358dea1b0 added LICENSE and updated README.md 2018-07-24 13:12:53 +02:00
Julian Hammer
305f00f859 reduced register use in throughput mode 2018-07-11 16:23:22 +02:00
Julian Hammer
6786c399ad added support for iaca analysis 2018-07-10 14:26:19 +02:00
Julian Hammer
3dac7d6795 added cli support for serialized instructions 2018-07-05 14:25:15 +02:00
Julian Hammer
a4fee9bc06 removed development code 2018-07-05 12:50:01 +02:00
Julian Hammer
654e2cd62f finalizing CLI, started with mem support 2018-07-04 16:53:06 +02:00
Julian Hammer
7a6d2e91ce fixed random selection and initial value constants 2018-06-27 15:16:18 +02:00
Julian Hammer
0349de9e64 first CLI :) 2018-06-26 15:11:35 +02:00
Julian Hammer
39659ee257 first steps towards a usable lib and cli 2018-06-25 18:30:23 +02:00
Julian Hammer
5e52c3fe17 major cleanup in tablegen 2018-06-22 16:14:36 +02:00
Julian Hammer
437eaadad4 code cleanups 2018-06-22 10:25:47 +02:00
Julian Hammer
239bf40d2c removed id from repr output 2018-06-15 14:38:36 +02:00
Julian Hammer
780880e264 yay, an upgrade of llvmlite fixed my issues 2018-06-15 12:38:56 +02:00
Julian Hammer
8d79aed894 added support of correct dstsrc register constraints to tablegen 2018-06-14 15:55:42 +02:00
Julian Hammer
e9cc5d2a00 fix for same source and destination registers 2018-06-14 14:23:37 +02:00
Julian Hammer
7859acdaa2 bench is now up to speed with op 2018-06-13 17:23:22 +02:00
Julian Hammer
990f020684 new register naming scheme 2018-06-12 15:29:57 +02:00
Julian Hammer
598f231138 this commit is a deadend 2018-06-06 17:11:50 +02:00
Julian Hammer
03e35d48ce slow progess, but progress nonetheless 2018-05-30 14:22:02 +02:00
Julian Hammer
0b4ef84285 work in progress 2018-05-25 17:08:33 +02:00
Julian Hammer
e30e8b0a38 first complete x86 tablegen workflow (very dirty) 2018-05-23 17:32:20 +02:00
Julian Hammer
cb131f1007 slow porgress 2018-05-17 18:12:32 +02:00
Julian Hammer
bf191f71d1 first steps into parsing tablegen output 2018-05-15 16:37:12 +02:00